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Computer Architectures and Operating Systems > Architectures - Intro and MIPS > Flashcards

Architectures - Intro and MIPS Flashcards

1
Q

What is a ZettaByte?

A

10^21 -> 2^70

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2
Q

How it is also called the instruction queue?

A

Front end

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3
Q

What does SoC stands for?

A

System on a Chip

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4
Q

Which are the major companies in the microprocessor field?

A

INTEL, ARM, AMD, IBM

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5
Q

In what the major companies of the microprocessor field are investing nowadays?

A

They are investing on multiprocessor systems on a chip (MPSoC) rather than on faster processors

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6
Q

Something about INTEL, AMD, ARM

A

Intel and AMD: they have the same instructions set but that set belongs to Intel

ARM: Samsung and Apple buy the interaction set from ARM and then they build the architecture

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7
Q

Which are the requirements for embedded computers?

A
  • real time performance
  • memory minimization
  • power consumption minimization
  • reliability constraints
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8
Q

Which are the classes of parallelism?

A

1) Data Level P: many data items can be operated at the same time
2) Task Level P: different tasks of work can operate independently

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9
Q

What do parallel architectures need in term of parallelism types? What do these types exploit?

A
  • Instruction level P: exploits DLP
  • Vector architectures and Graphic processor unit (GPU) to execute the same action on different data: exploits DLP
  • Thread Level P: both DLP and TLP
  • Request Level P: exploits parallelism among decoupled tasks
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10
Q

What is an ISA?

A

Instruction Set Architecture
= HOW the computer is seen by the programmer or the compiler

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11
Q

ISAs are different in term of…

A
  • processor performance and complexity
  • compiler complexity
  • code size
  • power consumption

These parameters have different weights depending on the product goal

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12
Q

How can we classify CPUs?

A

Based on:
- the type of their internal storage: where operands are stored
- the number of operands per instruction
- the number of memory operands per ALU instruction

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12
Q

Which types of instructions do we have in general?

A
  • arithmetic
  • logical
  • to move data
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13
Q

Which types of CPU do we have based on the storage and the number of operands? Make some examples

A
  • Stack (LIFO)
  • Accumulator
  • Register - memory: Intel 80x86 -> max 2 operands
  • Register - Register (load and store): ARM, MIPS -> max 3 operands

(pagina 3 per disegni)

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14
Q

Which type of memory does use load and store?

A

Register

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15
Q

Which are the things (characteristics) that characterize an instruction set?

A

1) Memory addressing (how data are read)
2) Operations in the instruction set
3) Type and size of operands
4) Instruction encoding

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16
Q

Memory addressing

A

It is an instruction set characteristic and it corresponds to how data are read.

It can be based on:
- little or big endian
- aligned or misaligned access

There are multiple addressing modes (another question) and the choice is influenced by statistics (how many times an instruction is used) and has important consequences in term of number of instructions CPU architecture complexity, Cycles Per Instruction CPI

17
Q

Little and Big Endian: example with 0x12345678

A
  • Little: it puts the Byte with the lower address to the least significant position
    -> it will be stored as 78 56 34 12
  • Big: it puts the Byte with the lower address to the most significant position
    -> it will be stored as 12 34 56 78
18
Q

Aligned or misaligned access

A
  • Aligned: simple hardware but waste of memory
  • misaligned: hardware and performance overhead are necessary
19
Q

when we use M[] to access the memory it will be the most significant or the least significant to be accessed?

A

Least one
example: 12 34 56 78 or 78 56 34 12 -> 78 and 12 accessed first

20
Q

Addressing Mode of Memory addressing with examples

A
  • Register mode: ADD R4, R3
  • Immediate mode: ADD R4, $3
  • Displacement mode: ADD R4, 100(R1) -> R4 + Memory[Content of R1 + 100]
  • Register deferred or indirect mode: ADD R4, (R1) -> in R1 there is a memory address and the content of that address is summed to R4
  • Indexed mode: ADD R4, (R1 + R2)
  • Direct or absolute mode: ADD R1, (1001) -> R1 + what we find at the address 1001
  • Memory indirect or memory deferred mode: ADD R4, @(R3) -> Mem[Mem[Regs[R3]]]
21
Q

Which is the goal in looking addressing statistics?

A

Make the common case faster and the rare one correct

22
Q

Operations in the instruction set

A

This is a characteristic of an instruction set and it corresponds to the type of operations we can perform using that set.
We can have:
- arithmetic and logical
- data transfer
- control
(the first three are available everywhere)
- system
- floating point
- decimal
- string
- graphics

23
Q

How do we specify the destination address?

A

with displacement mode with respect to the PC so that we save bits (good especially because the target instruction is often close to the source)
+ the code is position independent

24
Q

Type and Size of Operands

A

It is a characteristic of an instruction set.
Most frequently supported data are:
- char: 8 bit
- half word: 3 bytes
- word: 4 bytes
- double word: 8 bytes
- single precision floating point: 4 bytes
- double precision floating point: 8 bytes

25
Q

Instruction Encoding

A

It is one of the characteristics of an instruction set.
It depends on which instructions compose the IS and which addressing modes are supported.

If the number of modes is high there is a field in the instruction to specify the mode (called ADDRESS SPECIFIER), otherwise this info is encoded together with the opcode

If we have an encoding type that supports any number of operands and variable length we will have lower performance and minimum code size.
If we have a fixed number of operands and of length we will have maximum performance and larger code size

  • Variabile
    [Operation + @ of operands] + [Address Specifier 1] + [Address Field 1] + […] + [Address Specifier N] + [Address Field N] -> Specifier-Field Pairs
  • Fixed
    [Operation] + [Address Field 1] + [Address Field 2] + [Address Field 3] -> ARM, MIPS
    or we can have a single address specifier and then and address field for each operand or we can have a single address field and different address specifiers for each operand
26
Q

Which are the conflicting issues we find in choosing the instruction encoding?

A
  • the code size
  • the size of the IS, the # of addressing modes, the # of registers
  • the complexity of the fetch and decoding hardware
27
Q

What is the aliasing problem?

A

We can allocate variables to registers only if these are not stored in the heap memory

28
Q

Which are the three key words for an instruction set architecture?

A
  • At least 16 registers
  • orthogonality
  • simplicity
29
Q

What does MIPS stand for?

A

Microprocessor without Interlocked Pipeline Stages

30
Q

Characteristics of MIPS: fundamental, registers, data types, addressing modes

A
  • SIMPLE
  • designed for pipeline efficiency
  • designed for low power applications
  • register-register (load-store) instruction set
  • fixed instruction length 32 bits
  • 3 operands (3 registers or 2 registers and 1 immediate)
  • 32 General Purpose Integer Registers: $Rx
  • 32 Floating Point Registers: $Fx
  • special purpose registers such as PC, HI, L=…
  • Data Types: byte, half word, word, double word, 32 bit single precision floating point and 64 bit //
  • immediate of 16 bits
31
Q

MIPS addressing modes with examples

A
  • immediate field mode
  • displacement mode

Displacement mode examples:
- Register indirect: LD R1, 30(R2) -> in R1 is loaded the content of Mem[R2 + 30]
- Absolute addressing: LD R1, 64(R0) -> in R1 is put what there is inside Mem[64]

32
Q

MIPS instruction format

A
  • fixed 32 bit length -> WORD
  • opcode: 6 bits
  • types: Immediate, Register, Jump

I: opcode (6) + rs (5) + rt (5) + imm (16)

J: opcode (6) + offset (26, added to the PC)

R: opcode (6) + rs (5) + rt (5) + rd (5) + sa (5, shift amount) + function (6)

33
Q

Immediate in MIPS

A

signed number -> there will be the sign extension

34
Q

Which is the meaning of the function field of a MIPS instruction?

A

Instructions of type R are grouped based on the Function field value:
- Load and store
- ALU operations: all these operations are performed on operands held in processor registers
- Branches and jump: these instructions allow you to change the content of the PC and so to change the workflow
- Floating point
- Miscellaneous

35
Q

Which types of branches and jump there are in MIPS?

A
  • relative conditional branches
  • absolute unconditional branches
  • procedures with a return link
36
Q

What is an assembler program made of?

A

data section + code section

It has directives:
.data
…
.code
.global main

37
Q

How to obtain R7 = 0000 0000 C1AO FEDE?

A
  1. R7 = FFFF FFFF C1AO FEDE
  2. shift left logical 32 bits
    R7 = C1AO FEDE 0000 0000
  3. shift right logical 32 bits
    R7 = 0000 0000 C1AO FEDE
38
Q

LUI R1, 0x47
DADDUI R1, R1, 0x13

R1 = ?

A

R1 = 0x47000013

39
Q

What does the number 64 in MIPS64 mean?

A

64 registers, not number of 64 bits

Computer Architectures and Operating Systems (2 decks)

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