Architectures and Operating Systems

Question 1

List memory technologies charateristics:

Answer 1

Static RAM (SRAM):

Access Time: 0.5ns – 2.5ns
Cost: $500 – $1000 per GB

Dynamic RAM (DRAM):

Access Time: 50ns – 70ns
Cost: $10 – $20 per GB

Flash Superconductor Memory:

Access Time: 5,000ns – 50,000ns
Cost: $0.75 – $1 per GB

Magnetic Disk:

Access Time: 5,000,000ns – 20,000,000ns
Cost: $0.05 – $0.1 per GB

Ideal Memory:

Access Time: Same as SRAM
Capacity and Cost: Same as disk

The price decreases as you go down whereas the speed increases as you go up.

Question 2

What is Cache?

Question 3

What is cache hit?

Answer 3

A cache hit occurs when the data requested by the CPU is found in the cache, resulting in faster data access.

Question 4

What is cache miss?

Answer 4

A cache miss occurs when the requested data is not found in the cache, requiring the system to retrieve it from a slower memory level

Question 5

Formula for hit rate?

Answer 5

Hit rate = number of cache hits/total number of memory accesses *100

Question 6

Formula for miss rate?

Answer 6

Miss rate = 1 - hit rate

or

Miss rate = number of cache misses/total number of memory accesses * 100

Question 7

How can you measure cache performace?

Answer 7

AMAT (Average memory access time)

Question 8

Formula for AMAT?

Answer 8

AMAT = hit time + (miss rate * miss penalty)

A lower AMAT indicates better cache performance.

Question 9

What is miss penalty?

Answer 9

Miss penalty is the extra time required to fetch data from a lower memory level (like main memory) after a cache miss, including data retrieval and cache update time. At least 10 of clock cycles.

Question 10

Solve this problem:

Say hit rate is 98%, hit time is one clock cycle and the miss penalty is
50 clock cycles. What is AMAT?

Answer 10

AMAT = hit time + (miss rate * miss penalty)
AMAT = 1 (always 1) +( 0.02 (100-98/100) * 50) = 2

Question 11

What are the two types of locality that improve cache performance?

Answer 11

Temporal Locality: Recently accessed items are likely to be accessed again soon. Instructions within a loop or frequently accessed variables.

Spatial Locality: Items near recently accessed data are likely to be accessed soon. Sequential instructions or array elements accessed in order.

Question 12

What is direct mapping?

Answer 12

Direct mapping assigns each memory location to exactly one cache block based on the index calculated using modulo division:

Cache Index=Memory Address mod 2k

where k is the number of index bits.

Question 13

What is hit time?

Answer 13

Hit time is the time required to access data from the cache, including the time to check the cache tags and retrieve the data. Usually 1-3 clock cycles.

Question 14

What is a fully associative cache?

Answer 14

A fully associative cache allows any memory address to be placed in any cache block. It requires checking all cache tags for a match, which increases complexity and cost.

Question 15

What is a set associative cache?

Answer 15

A set associative cache divides the cache into multiple sets, each containing a fixed number of blocks. A memory address maps to a specific set, and data can be placed in any block within that set.

Question 16

How does set associativity balance between direct and fully associative caches?

Answer 16

Set associativity offers a compromise by limiting the number of possible cache blocks a memory address can map to, reducing complexity compared to fully associative caches while increasing flexibility over direct-mapped caches.

Question 17

What are the components of a memory address in a set associative cache?

Answer 17

Tag: Identifies the specific memory block.
Set Index: Determines which set the data belongs to.
Block Offset: Specifies the exact byte within the cache block.

Question 18

What is the valid bit in a cache block?

Answer 18

The valid bit indicates whether the data in a cache block is valid (1) or invalid (0). Initially, all valid bits are set to 0.

Question 19

What happens during a cache hit?

Answer 19

The CPU sends the address to the cache controller.
The cache controller uses the index to locate the set.
It checks the valid bit and compares the tag.
If it matches, the data is sent to the CPU.

Question 20

What steps occur during a cache miss?

Answer 20

The CPU requests data from the cache.
The cache controller detects a miss.
Data is fetched from the main memory.
The data is copied into the appropriate cache block.
The valid bit is set to 1

Question 21

How is the cache size calculated for a direct-mapped cache?

Answer 21

For example:
Number of Blocks: 32
Block Size: 1 byte
Address Size: 16 bits

Each block requires:

Tag: 11 bits (16 - 5 index bits (5 bits comes before all the index added up)
Valid Bit: 1 bit
Data: 8 bits

Total Cache Size:
32×(11+1+8)=32×20=640 bits

Question 22

What is a replacement strategy in associative caches?

Answer 22

When all blocks in a set are valid, the least recently used (LRU) block is replaced to make space for new data.

Question 23

What is a common issue with direct mapping?

Answer 23

If multiple frequently accessed memory addresses map to the same cache block, it can cause excessive cache misses, reducing cache efficiency.

Question 24

How does a fully associative cache address the issue of direct mapping?

Answer 24

By allowing any memory address to be placed in any cache block, fully associative caches can better utilise cache space and reduce conflicts, leading to fewer cache misses.

Question 25

How does set associativity optimise cache performance?

Answer 25

Set associativity reduces the complexity of fully associative caches by dividing the cache into sets and allowing multiple blocks per set, thus balancing speed and flexibility.

Question 26

What is the valid bit used for in cache blocks?

Answer 26

The valid bit indicates whether the data in a cache block is valid (1) or invalid (0). It helps determine if a cache block contains meaningful data