Application Processor Part 1 Flashcards
What is the Arithmetic/ Logic Unit?
Operate on values stored in the Registers
What is a register?
Group of flip-flops with common clock used to store binary data
What is the instruction register?
Hold current instruction.
What is the instruction pointer?
Hold the address of the next instruction in memory
What is RISC?
Reduced Instruction Set Computer. Only execute one instruction at a time but usually take one machine cycle.
What is CISC?
Complex Instruction Set Computer. Executes an instruction over a span of two to ten machine cycles but can execute multiple steps of each instruction at the same time.
What is the CORTEX A series used in?
Smartphones, digital TV, servers and networking.
What is the CORTEX R series used in?
Automotive Braking systems, powertrain solutions, and mass storage controller.
What is the CORTEX M series used in?
Micro controllers, mixed signal devices, and smart sensors
What are the main features of ARMv7 A architecture?
- Large uniform register file
- 32 bit processor
- Instructions are 32 bit long
- Good speed/power consumption ratio
- High code density
What are the enhancements to basic RISC features?
- Control over ALU and shifter for every data processing operation to maximize there usage.
- Auto-increment and auto-decrement addressing modes to optimize program loops
- Load and store multiple instructions to maximize data throughput
- Conditional execution of instruction to maximize execution throughput.
What does the ARM Core Registers do?
- The general purpose registers hold either data or address.
- All registers are 32 bits
- In user mode 16 data registers and 2 states registers are visible
What is the function of register r13?
Stack pointer (can also be used as GPR)
What is the function of register r14?
Link register (where return address is put whenever a subroutine is called and can be used as GPR)
What is the function of register r15?
Program counter
What are the two status registers?
- CPSR : current program status register
- SPSR : saved program status register
What are the flags of CPSR?
- Condition code flags
- Sticky overflow flag
- J bit
- Interrupt disable bits
- T Bit
- Mode bits
What are the flags of condition code flags?
- N : Negative result from ALU
- Z : Zero result from ALU
- C : ALU operation Carried out
- V : ALU operation oVerflowed
What does flag N of condition code flags do?
- Logical Instruction : No meaning
- Arithmetic Instruction : Bit 31 of the result has been set. Indicates a negative number in signed operations
What does flag Z of condition code flags do?
- Logical Instruction : Results in all zeros
- Arithmetic Instruction : Result of operation was zero
What does flag C of condition code flags do?
- Logical Instruction : After Shift operation ‘1’ was left in carry flag
- Arithmetic Instruction : Result was greater than 32 bits
What does flag V of condition code flags do?
- Logical Instruction : No meaning
- Arithmetic Instruction : Result was greater than 31 bits. Indicates a possible corruption of the sign bit in signed numbers
What does the processor mode determines?
- Which registers are active
- Access rights to CPSR register itself
What is privileged and non-privileged?
Privileged : full read-write access to CPSR
Non-privileged : only read access to the control field of CPSR but read-write access to the condition flags.
What are the basic operating modes?
- User
- FIQ
- IRQ
- Supervisor
- Abort
- Undef
- System
What does User mode do?
Unprivileged mode under most tasks are run
What does FIQ mode do?
Entered when a high priority (fast) interrupt is raised
What does IRQ mode do?
Entered when a low priority (normal) interrupt is raised
What does Supervisor mode do?
Entered on reset
What does Abort mode do?
Used to handle memory access violations
What does Undef mode do?
Used to handle undefined instructions
What does System mode do?
Privileged mode using the same registers as user mode
What is Banked Registers?
- 20 registers are hidden from program at different times
- Available in certain modes
- Maps one-to-one onto a user mode register
What is the saved program status register (SPSR)?
- SPSR is associated with privileged mode except system mode
- Used to save the state of CPSR when the privileged mode is entered
What is mode changing?
- By writing directly to CPSR or by hardware when the processor responds to exception or interrupt
- To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers
What is included in the ARM instructions set?
- Data processing instructions
- Data transfer instructions
- Block transfer instructions
- Branching instructions
- Multiply instructions
- Software interrupt instructions
What is data processing?
Manipulate data - MOVE instructions - Arithmetic instructions - Logical instructions - Comparison instructions Suffix S on data processing instructions updates flags in CPSR
How does data processing instructions work?
- Operands are 32 bit wide; come from registers or specified as literals in the instruction itself
- Second operand sent to ALU via barrel shifter
- 32 bit result placed in register; long multiply instruction produces 64 bit result
What is move instruction?
MOV Rd, N
- Rd: destination register
- N: can be an immediate value or source register
- mov r7, r5
MVN Rd, N
- Move into Rd not of the 32 bit value from source
What does the barrel shifter enables?
- Enables shifting 32 bit operand in one of the source registers left or right by a specific number of positions within the cycle time of instruction
- Shift left, shift right, rotate right
- Facilitates fast multiply, division
What is arithmetic instruction?
Implements 32 bit addition and subtraction
- SUB r0, r1, r2
- Subtract value stored in r2 from that of r1 and store in r0.
What is arithmetic instruction with barrel shifter?
Increases the set of possible available operations
What are multiply instructions?
Multiply contents of a pair of registers - generate 64 bit results
What is multiply and accumulate?
Result of multiplication can be accumulated with the content of another register. Signal processing - Filtering - Communications - Error control codes
What is Logical Instructions?
Bit wise logical operations on the two source registers.
What is compare instructions?
Enables comparison of 32 bit values, update CPSR flags but do not affect other registers
What is data transfer instructions?
- Load/store instructions
- Used to move signed and unsigned Word, Half Word and Byte to and from registers
What is Multiple Register Transfer?
- Load-store multiple instructions transfer multiple register contents between memory and the processor in a signal instruction
- More efficient for moving blocks of memory and saving restoring context and stack
- Increase interrupt latency
What are block transfer instructions?
- Load/store multiple instructions (LDM/STM)
- Whole register bank or a subset copied to memory or restored with single instruction
What is swap instruction?
Exchanges a word between registers.
- Two cycles but single atomic action
How to modify status registers?
- Indirectly
- MSR moves contents from CPSR/SPSR to selected GPR
- MRS moves contents from selected GPR to CPSR/ SPSR
- Only in privileged mode
What are control flow instructions?
- Branch instructions
- Conditional branches
- Conditional execution
- branch and link instructions
- Subroutine return instructions
What is branch instruction?
- B label : address label is stored in the instruction as a signed pc-relative offset
- B : Branch has a condition associated with it and executed if condition codes have the correct value
What is conditional execution?
The conditional execution applies not only to branches but to all ARM instructions.
- Each data processing instruction prefixed by condition code - 16 conditions
Data Processing Instructions overview?
Conditional codes + data processing instructions + barrel shifter = powerful tools for efficient coded programs
What are the features of ARM instruction set?
- Load/Store architecture
- 3 address data processing instruction
- Conditional execution
- Load/store multiple registers
- Shift and ALU operation in single clock cycle.
