AI Hardware

Question 1

PCIe stands for

Answer 1

PCI express

Question 2

PCI stands for

Answer 2

Peripheral component interconnect

Question 3

Bus

Answer 3

a communication system that transfers data between components inside a computer, or between computers.

Question 4

At a high level physical level what does the term “bus” mean?

Answer 4

a path between the components of a computer

Question 5

What do you insert into a PCI slot?

Answer 5

A PCI card (that I guess is or is attached to some peripheral like a video card, sound card, etc)

Question 6

PCI was common when?

Answer 6

From 1993 to 2007

Question 7

PCIe definition

Answer 7

A dual-slot card design by Nvidia that requires no connection to the power supply, unlike the PCI cards

Question 8

NVidia NLink

Answer 8

a high-bandwidth, energy-efficient interconnect that can transfer data up to ten times faster than PCIe

Question 9

SXM2

Answer 9

A card slot design that allows the GPU to communicate either with each other or to the CPU through Nvidia’s NVLink

Question 10

Tesla P100 price in 2016

Answer 10

Roughly $6k to roughly $10k depending on the type of interconnect

Question 11

Dollars per TFLOPs of P100 in 2016?

Answer 11

~$1200 to $1800 depending on the variant selected for the memory and the interconnect

Question 12

What Tesla GPU was of the generation before P100?

Answer 12

Tesla K40

Question 13

How much did a K40 cost? [ostensibly when it was in season]

Answer 13

~$2350 per TFLOP

Question 14

A100 die area (aka die size)

Answer 14

826 square mm

Question 15

A100 transistor count

Answer 15

54 billion

Question 16

Estimate of how many dies fit on an A100 wafer

Answer 16

64

Question 17

What is the relationship between wafers and and a die?

Answer 17

A wafer is the round slice that the individual dice (dice is plural of die) are printed/somehow constructed on on. Each die is then sliced off from the wafer

Question 18

Warps/wavefronts

Answer 18

. Warps/Wavefronts: In NVIDIA GPUs, for example, threads are organized into warps, which are sets of 32 threads that execute the same instruction at the same time but on different data.