9.1 - The Fetch-Decode-Execute Cycle Flashcards
What is the Fetch–Decode–Execute (FDE) cycle?
It is the process by which a computer runs programs by repeatedly fetching an instruction from memory, decoding it into its constituent parts (opcode, mode, and data/address), and executing it.
What are the three main steps in the FDE cycle?
The three steps are: 1) Fetch – retrieving the next instruction from memory, 2) Decode – determining what the instruction means, and 3) Execute – carrying out the instruction.
What is the main shortcoming of the traditional FDE cycle?
In the traditional FDE cycle, each instruction must be completely fetched, decoded, and executed before the next one is processed, leading to inefficiency with one instruction taking three clock cycles.
How does the three-stage pipeline method improve instruction throughput compared to the traditional FDE cycle?
It overlaps the processing stages so that while one instruction is being executed, the next can be decoded and the following one fetched simultaneously, thus reducing idle time.
What challenge does the three-stage pipeline face with branch operations?
When a branch instruction occurs, the pipeline may fetch instructions from the wrong location, causing delays or a pipeline flush as the correct execution path is re-established.
What is the superscalar method in CPU design?
The superscalar method allows the CPU to fetch, decode, and execute multiple instructions simultaneously by using multiple execution units, thereby increasing performance.
How do superscalar processors handle branching to maintain performance?
They use branch prediction to guess which path the branch will take, allowing the processor to continue fetching and executing instructions. If the prediction is wrong, the pipeline is flushed and restarted from the correct branch.
What are the steps for debugging machine code in a Simple Computer Architecture (SCA) using the FDE cycle?
1) Reset all registers to 0. 2) Load the Instruction Register (IR) with the contents at the memory address in the Program Counter (PC). 3) Increment the PC by 1. 4) Decode and execute the instruction in IR (updating registers as needed). 5) Repeat until a HALT instruction is encountered.
