8a: Internal hardware components Flashcards

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1
Q

what is the stored program concept

A
  • the program the proccesser is executing is kept in main memory along with the data the program needs
  • the processer fetches one instruction at a time (serially) from main memory and executes it
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2
Q

explain the role of the processer

A
  • executes instructions and controls the operation of all components
  • executes instructions by repeating 3 operations: Fetch Decode Execute
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3
Q

what is the role of the main memory

A
  • holds the current programs that are being executed
  • hold current data being processed
  • temporary memory: loses its contents when the computr turns off
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4
Q

what is the role of the secondary memory and give examples

A
  • permanent storage of data and programs
  • eg, HDD and CD drive
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5
Q

what are the 3 different buses

A
  1. address
  2. control
  3. data
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6
Q

describe and explain the control bus

A
  • bi-directional bus
  • used to transmit command, timing and specific status information between system components
  • timing signals ensure that the various components operate in synchrony
  • command signals specificy operations to be performed
  • status signals indicate information about how things are going, like wether a task is done or not
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7
Q

explain the following control lines:
1. memory write
2. memory read
3. I/O write
4. I/O read
5. bus request

A
  1. causes data on data bus to be written to addressed location
  2. causes data from addressed location to be placed on data bus
  3. causes data on data bus to be output to the addressed I/O port
  4. caused data from the addressed I/O port to be placed on the data bus
  5. indicates a component needs to gain control of the system bus
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8
Q

describe and explain the data bus

A
  • typically consists of 8, 16 or 32 seperate lines
  • bi-directional line for moving data and instructions between system components
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9
Q

explain the importance of the width of the data bus

A
  • width of data bus is a key factor to determing overall system pecformance
  • if data bus is 8 bits wide and each instruction is 16 bits long then the processor must access main memory twice during each instruction cycle
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10
Q

explain the address bus

A
  • when the CPU needs to read or write data, it uses the address bus to specify the memory location its interested in
  • the width of the address bus determins the maximum amount of memory the computer can access
  • the CPU uses the adress bus to fetch instructions and data from memory, enabling the execution of tasks
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11
Q

what are five factors affecting processors performance

A
  • width of address bus
  • multicore processor
  • clock
  • word length
  • cache memory
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12
Q

full explanation

explain the steps of the fetch execute cycle

A
  1. the contents of the program counter (the adress of the next instruction) is placed into the memory address register
  2. the adress is sent from the MAR along the adress bus to the main memory. The instruction at that adress is found and returned along the data bus to the memory buffer register
  3. at the same time the contents of the program counter is increased by 1, to reference the next instruction to be executed
  4. the MBR loads the current instruction register with the instruction to be executed
  5. the instruction is decoded an executed
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13
Q

what are the 2 different types of architecture

A
  • Von Neumann
  • Harvard
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14
Q

compare Von Neumann architecture to Harvard architecture

A
  • VN is an ancient computer architecture whereas H is modern
  • Vn has same physical memory address for instructions and data whereas H has seperate physical memoy adresses for instructions and data
  • in VN it uses one bus for both data and instructions whereas in H it uses seperate buses
  • in Vn two clock cycles are required to execute a single instruction whereas in H a single cycle is needed
  • VN is cheaper
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15
Q

give the definition for:

processor

A

a device that carries out computation data by following instructions

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16
Q

give the definition for:

main memory

A

RAM
stores data and instructions that will be used by the processor

17
Q

give the definition for:

read only memory (ROM)

A

stores data that can be read from but not written to

18
Q

give the definition for:

bus

A

microscopic parallel wires that transmit data between internal components

19
Q

give the definition for:

data bus

A

transfers the data between the processor and memory

20
Q

give the definition for:

word length

A

the number of bits that can be addressed, transferred or manipulated as one unit

21
Q

give the definition for:

address bus

A

used to specify a specific address in memory so that the data bus can access it

22
Q

give the definition for:

control bus

A

controls the flow of data between the processor and other parts of the computer

23
Q

give the definition for:

von neumann architecture

A

a technique for building a processor where data and instructions are stored in the same memory and accessed via buses

24
Q

give the definition for:

harvard architecture

A

technique for building a processor that uses seperate buses and memory for data instruction

25
Q

give the definition for:

arithmetic logic unit (ALU)

A

part of the processor that performs the arithemtic and logical operations

26
Q

give the definition for:

clock

A

a device that generates a signal used to synchronise the components of a computer

27
Q

give the definition for:

register

A

a small section of temporary storage that is part of the processor. Stores data or control instructions during the fetch-decode-execute cycle

28
Q

give the definition for:

status register

A

keeps track of the various functions of the computer such as if the result of the last calculation is positive or negative

29
Q

give the definition for:

current instruction register (CIR)

A

register that stores the instructions that the CPU is currently decoding/exectuting

30
Q

give the definition for:

program counter (PC)

A

register that stores the address of the next instruction to be taken from main memory into the processor

31
Q

give the definition for:

memory buffer register (MBR)

A

register that stores data to or from the main memory

32
Q

give the definition for:

memory address register (MAR)

A

register that stores the location of the address that the CPU wishes to access

33
Q

give the definition for:

bus width

A

the number of bits that can be sent down a bus in one go

34
Q

give the definition for:

multi-core

A

a chip with more than 1 processor

35
Q

give the definition for:

cache

A

a high speed temporary area of memory

36
Q

explain why the data bus must be bidirectional

A
  • it is responsible for carrying data to and from the CPU and memory
  • it has to read and write data