5. Logic Design Flashcards
Why do we use binary (on/off) as opposed to ternary (full, half, off)?
The computer could misread a shift from off to full as a half state.
What is meant by a combinational logic circuit?
A circuit whose output only depends on the current inputs.
What is meant by a sequential logic circuit?
A circuit whose outputs depends on the current inputs and previous inputs (requires memory).
Give three examples of minimally functionally complete gates.
Any from:
{AND, NOT}
{OR, NOT}
{NAND}
{NOR}
A multiplexer takes in three inputs, a, b and S.
When S is on, value a is outputted. When S is off, value b is outputted.
What is the simplified combinational circuit for a multiplexer?
a.S + b.{not S}
Construct a 1 bit adder for an arithmetic n-bit adder.
The adder requires three inputs (a,b and a carry c) and two outputs (the sum s and the output carry o).
Then, considering the sum and carry independently,
s = ~a.~b.~c + ~a.b.~c + a.~b.~c + a.b.c
c = b.c + a.c + a.b
Explain how a ripple carry adder is formed, stating the minimum total gate time for an 8-bit adder.
A ripple carry adder is made up of a set of 1-bit adders.
Minimum adder is:
bit 1 is half-adder: 2 gates
bit 2-7 is full adders: 3 gates * 6 = 18 gates
bit 8 is adder (but no carry) : 2 gates.
Thus, total is 22 gates.
What affects the propagation delay?
The technology, delay through each gate and number of gates driven by a gate’s output.
If there are n feedback signals in a sequential logic circuit, how many states are there possible?
2n states
A sequential circuit with an original input and a feedback input OR’ed together has what function?
Outputs 1 if there has ever been a 1 given to the circuit.
In a NOR SR-latch, what happens when IN1 has the following sequence of bits passed to it: 0110?
[Assume IN1, IN2 and OUT2 are 0 to begin]
0: No change
1: OUT1 -> 0, OUT2 -> 1
1: No change
0: No change
In a NOR SR-latch, with a reset, set and outputs Q and ~Q, what does setting the reset line to 1 do?
Setting the reset line sets Q to be 0 (likewise the set line sets it to 1)
Give an example of a circuit that causes a glitch due to asynchronicity.
(~~~a).a
To begin, a is 0, so ~~~a is 1. When a 1 signal is sent in, a becomes 1, and so the output is 1. Then, the ~~~a becomes 0 and it quickly flicks back to 0.
How are glitches prevented in a SR-latch?
A clock is added (set of ands between the dividing ‘NOT’ and the latch itself).
State the common name for a clocked SR latch?
D flip-flop
