4.7.3 The Processor and its Components Flashcards

1
Q

What is the overall meaning of this topic?

A

It is the internal hardware component of the computer that is responsible for executing the instructions of programs.

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2
Q

What components are there?

A

ALU, CU, Clock, Registers.

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3
Q

Define the ALU.

A

Arithmetic Logic Unit.

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4
Q

What is the ALU responsible for?

A

ALU is responsible for performing arithmetic calculations and logic operations.
e.g addition…, logical bitwise operations, comparisons of values, shifting…

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5
Q

Define the CU.

A

Control Unit.

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6
Q

What is the CU in charge of?

A

CU is in charge of organising the sequence in which program instructions are executed, followed by decoding the instructions.
CU is also responsible for directing the operations of all the other components of the processor.

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7
Q

What does decoding mean in the CU?

A

Decoding means analysing the opcode and operand of the instruction.

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8
Q

What are some tasks of the CU?

A
  • Uses control signals to enable data to be read from and written to main memory.
  • decodes instructions that the processor will execute to determine what needs to be done.
  • organises sequence of micro-operations that need to be performed in order to carry out instruction.
  • Uses control signals to determine operation the ALU will carry out.
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9
Q

What does the Clock do?

A

The Clock generates a timing signal which changes at a regular frequency. This is used to synchronise communication between the components of the processor and the rest of the computer system.

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10
Q

What is the clock speed measured?

A

It is measured in Hertz.

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11
Q

What are Registers?

A

Registers are small storage locations used to hold data temporarily. They have high read and write speeds.

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12
Q

What are General Registers?

A

General Registers are registers that can be used as storage for any data that is required by instructions during execution.

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13
Q

What are Dedicated/Special Registers?

A

They are specific registers assigned to store specific information.

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14
Q

Give the names of the Special Registers.

A

PC, CIR, SR, MAR, MDR/MBR

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15
Q

What is the PC and what does it do?

A

Program Counter.
Hols the memory address of the next instruction to be executed by the processor in the FDE cycle.

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16
Q

What is the CIR and what does it do?

A

Current Instruction Register.
Holds the current instruction that is currently being executed by the processor.

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17
Q

What is the SR and what does it do?

A

Status Register.
Contains a number of bits. Each bit within the SR acts as a flag to indicate if an error or exception has occurred or to enable or disable interrupts.

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18
Q

What is the MAR and what does it do?

A

Memory Address Register.
Temporarily stores the memory address of a memory location in main memory that the processor needs to access, or to be read from or written to.

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19
Q

What is the MDR/MBR and what does it do?

A

Memory Data Register/ Memory Buffer Register.
Temporarily stores the contents of a memory location that has been read from or data that is to be stored.

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20
Q

What does FDE stand for?

A

Fetch Decode Execute Cycle.

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21
Q

What happens in the Fetch stage of FDE?

A

Fetch - CPU fetches data and instructions from RAM then stores in registers.
1. PC has the next instruction to execute.
2. PC copied to MAR, then copied to address bus.
3. Address bus carries address to RAM.
4. Data bus carries the instruction stored in the address location to the CPU, saved in the MDR/MBR.
5. PC increments by 1.
6. MDR/MBR is copied to the CIR.

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22
Q

What happens in the Decode stage of FDE?

A

Decode - CPU works out what the instruction means.
1. CU decodes the instruction in the CIR. Splitting into opcode and operand, determining the type of instruction or if any additional data is needed for the instruction to execute.

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23
Q

What happens in the Execute stage of FDE?

A

Execute - Data processing happens. Once a cycle has completed, another starts.
1. Instruction is executed. e.g arithmetic instruction executed in ALU, result stored in ACC or back in RAM.

24
Q

What happens between each FDE Cycle?

A

Between each execute and fetch stage of cycle, the contents of status register is checked if there is a need for interrupts.

25
Q

Define Instruction Set.

A

Describes the commands a processor can perform. Defines all the instructions and how they are represented.

26
Q

Do different types of processors have the same instruction set?

A

Different types of processors have their own instruction sets, but may perform similar or identical operations.

27
Q

What two components make up an instruction?

A

Opcode and Operand.

28
Q

What is an Opcode?

A

The opcode is the actual command that includes the basic machine operation and the addressing mode.

29
Q

What is an Operand?

A

The operand is the value of the instruction or the address in memory.

30
Q

What is an addressing mode?

A

An addressing mode is usually 2 bits of data that tells it the way the operand is interpreted.

31
Q

What are the 2 types of addressing modes?

A
  1. Immediate Addressing (00)
  2. Direct Addressing (01)
32
Q

What does it mean if the opcode is immediate addressing?

A

The operand will be treated as a value. Or can be shown as a value using the # sign.

33
Q

What does it mean if the opcode is direct addressing?

A

The operand will be treated as an address. such as a memory location.

34
Q

What are the types of instructions?

A
  1. Data transfer - store, load
  2. Arithmetic Operations - add, subtract
  3. Comparison Operations - compare 2 values
  4. Logical Operations - AND, OR, NOT
  5. Branch - conditional(if), unconditional(break)
  6. Shift Operators - shifts binary in register
35
Q

What are some low Level language characteristics?

A
  • uses the specific instruction set of a processor, the instruction set is defined by the manufacturer.
  • non portable -> does not run with different processors.
  • allows programmers to have individual control over specific components or registers -> higher efficiency.
  • programs require less memory and execute faster than high level language program.
36
Q

What are the 2 types of low level languages?

A
  1. Machine Code
  2. Assembly Code
37
Q

What is machine code?

A

Machine code is made up of binary 1s and 0s -> does not need to be translated before running.

It is difficult for humans to write, read, debug and fix problems, usually hexadecimal is used to represent binary digits as easier to understand.

38
Q

What is Assembly code/language?

A

They are mnemonics for instructions (represent the binary equivalent in machine code)
They need to be translated - assembling by a program: Assembler.
Can directly interact with main memory by ‘calling’ memory locations.

39
Q

What are some advantages of low level languages?

A
  • allows the programmer to create optimised programs
  • allows programmer to more directly control how resources are used in computer system
  • allows programmer to make use of specific registers, for greater efficiency
40
Q

What are some disadvantages of low level languages?

A
  • more difficult to write in low level than high level
  • not portable, specific to instruction set
  • do not have libraries or functions that can be imported like high level languages : programmers have to write every process themselves
41
Q

Space for assembly language…

A
42
Q

What are Interrupts?

A

Interrupts are signals sent to the processor to temporarily halt its current task, allowing it to execute an Interrupt Service Routine(ISR).
After handling the interrupt, the processor resumes its previous task.

43
Q

What are the two ways of interrupts?

A
  1. Polling
  2. Interrupts System
44
Q

What is Polling?

A

In Polling : The CPU checks with each peripheral device for attention (even when some devices do not require attention) -> inefficient process.

45
Q

What is an Interrupts System?

A

A device sends a signal on the control bus to the CPU to indicate it requires attention.

46
Q

What is the process of a typical FDE cycle including the interrupts?

A

Fetch -> Decode -> Execute -> Interrupts

During the Interrupts stage: the CPU checks for signals from the control bus ; if there is an interrupt, the FDE cycle stops and an Interrupt Service Routine (ISRs) is run -> handles the interrupt

47
Q

What is the problem created with the interrupts system?

A

If the PC is changed to run the ISR, how will the CPU know where to continue after the interrupt?

48
Q

What is the solution to the problem created by the interrupts system?

A

A stack.

The contents of the PC are copied to the stack, and the ISR replaces the PC. So the ISR is run. After running the ISR, the contents of the stack are copied back to the PC so the CPU can continue where it left off.

49
Q

What are the priorities for the ISR?

A

The most updated / new interrupt will always execute first, even when running another ISR.

50
Q

What are some types of interrupts?

A
  1. Hardware
    - power button pressed
    - memory parity error
  2. Software
    - illegal instruction
    - arithmetic overflow
    - new log - on request
  3. Input Output
    - buffer nearly empty
    - signal the completion of data transfer to/from a device
51
Q

What are the Factors affecting FDE cycles?

A
  • clock speed
  • cache size
  • number of cores
  • bit of address bus
  • bit of data bus
  • word length
52
Q

How does the factor clock speed affecting FDE cycles?

A

Clock speed is an electronic oscillator that produces a signal to synchronise the operation of the processor.
The faster the clock speed, the faster the speed of instructions being executed.
Unit is GHz.
- Overclocking -> when the clock speed is more than the manufacture’s recommended may lead to overheating and shorter lifespan of the device.

53
Q

How does the factor cache size affect FDE cycles?

A

Cache is a relatively small capacity set of locations used to store frequently used data or instructions. Is volatile like RAM.
Levels of Cache ->
L1 smallest and fastest cache, sits on each core ; L2 shared by cores ; L3 slower but larger, on processor or motherboard ; L4 placed on or near processor.
Cache reduces the time it takes for instructions and data to pass through system registers, so more efficient.

54
Q

How does the factor number of cores affect FDE cycles?

A

The more number of cores, the more instructions it can execute simultaneously so more efficient.
However other factors can also affect the efficiency of multicore systems.
Parallel Processing - dividing a computational task into subtasks that can be processed in parallel - only on multicore systems.

55
Q

How does the factor address bus width affect FDE cycles?

A

The width of the address bus determines the number of bits that can be used to form an address of a memory location.
The larger the width of the address bus, the more memory locations can be addressed.
It reduces the reliance on slower virtual memory.
If the width of the address bus is n bits, then there are 2 ^ n of distinct memory addresses available for memory.

56
Q

How does the factor data bus width affect FDE cycles?

A

The width of the data bus determines the number of bits that can be transferred to or from in one operation.
The larger the size of the data bus, the higher the performance of the processor.
The greater the width, the more data can be transferred between the internal components simultaneously.
If the width of data bus is n bits, then n bits can be transferred between the internal components in one operation.

57
Q

How does the factor word length affect FDE cycles?

A

The word length refers to the amount of data that can be handled at one time by the processor.
A word is a group of bits that is treated as a single unit by a processor. Words can be used for representing both instructions and data.
The larger the size of the word, the more amount of data can be transferred to CPU in one pass.
The larger the word length, the less fetches of data from main memory, carrying out instructions faster.