4.7 Computer organisation and architecture Flashcards
Describe 3 box model (Von Nueman)
Processor, Main memory and Input/Output connected by buses.
What is main memory
Memory directly addressable by processor
What is RAM
Volatile memory that can be read or written to in any order
What is an I/O controller and what does it do ?
Circuit board connected to the bus and I.O device to communicate with processor (Eg. correct I and V)
What are system buses and what do they do ?
Parallel wires connecting components as signals.
What are data buses and what do they do ?
Bi directional buses carrying data between components.
What are address buses and what do they do ?
Uni directional bus btwn address memory and I/O locationsaway from the processor
What are control buses and what do they do ?
Bi directional bus relaying control signals btwn components (Eg. keeping clock in time.)
What is the stored programme concept ?
Program must reside in main memory to be executed. Fetched and decoded sequentially.
Harvard Vs. Von Nueman
Harvard:
Faster, Multitasking and no competition for bus.
Good for stand alone machines as fixed proportions of capacity for processing instructions and data.
Von Nueman:
Cheaper
Adaptable to change as all in main memory
Good for general purpose as no fixed proportions for capacity processing instructions and data.
Fetch (Fetch decode execute cycle)
PC holds address of next instruction to be executed.
Copies address to MAR.
MAR (Address bus) —> Main memory
Instruction held at address (Data Bus)
—> Memory Buffer Register
Pc increments to hold address of next instruction
Decode (Fetch decode execute cycle)
MBR contents copied to CIR and decoded by CU.
Execution - What does the ALU do ?
Logic or Calculations
What is the clock and what does it do ?
Continuous sequence of pulses to step CU through its operations
What is a Register and what does it do ?
Fast, on-processor, temporary storage of binary values.
What is an instruction set and what does it do ?
Binary code for machine operations the processor performs. Processor reads machine code. Interpreted into assembly language for readability based on processors instruction sets.
Name 4 components that effect processor performance
ANY FROM : No. Cores . Cache memory, clock speed, word length, data bus width and address bus width.
How does the no. cores effect processor performance
Each can perform its own FDE cycle independently so each core is allocated to running a different application allowing it run faster.
How does the amount of cache memory effect processor performance ?
Cache has higher read and write speeds so more cache reduces fetches required to retrieve info from main memory saving time.
How does clock speed effect processor performance ?
Freq. of pulses that keep machine in time. Higher freq. pulse –> higher freq. FDE cycle.
How does word length effect processor performance ?
Word (group of bits treated as one unit by processor).
Word Length (number of bits per word).
Higher word lengths –> more bits transferred.
How does address bus width effect processor performance ?
Increase width (no. parallel wires) –> Increase range of addresses –. increase addressable memory.
Each wire doubles addresses available.
How does data bus width effect processor performance ?
Increase width –> Increase volume of data transfer at any one time allowing processor to fetch more data –> reduces no. FDE cycles req.
What is an interrupt?
A signal requesting the attention of the processor that is detected as a change in the status register btwn. F=E in FE cycle.
