2506 Midterm Review Flashcards
format for R-type instruction
op rs rt rd shamt funct
format for I-type load/store instruction
op rs rt 16-bit imm
format for J-type branch instruction
op 26-bit imm
rt register
2nd source register
rs register
1st source register
rd register
destination register
load command specifies destination
first
store command specifies destination
last
beq
branch on equal
bne
branch on not equal
instructions that take 2 registers
addi
lw
beq
instructions that take only an immediate
j
instructions that take 3 registers
add, or
how long are MIPS instructions
32 bits
shamt
shift amount
for an I-type instruction, where is content written?
in $rt
how is the appropriate address calculated from an I-type instruction?
the contents of $rs is fetched to the ALU and added to the immediate field
how many bits is an opcode?
6 bits
what does a memory unit do?
store instructions and data values
what does a register do?
store instructions and data values within the processor
what does an ALU do?
implement basic operations
what do multiplexors do?
allow selection among different choices for operands and data values
what does a control unit do?
decode instructions and manage other elements during execution
what does a sign extension unit do?
widen values from 16 to 32 bits
what does a shift unit do?
perform multiplication by a power of 2
What inputs does a memory unit take?
a 32 bit address that will be accessed
a 32 bit data value to be written to that address (when memwrite is on)
What is the output of a memory unit
32 bit value that was read from the given address
what are the 2 controls within a memory unit?
MemWrite
MemRead
Both contain a single bit and indicate whether or not the address should be written to or read from
where are registers organized in the MIPS architecture?
a register file
what are the register file inputs?
two 5 bit numbers specifying the two registers to be read from
one 5 bit register number to be written to
32 bit data value to be written into the target register
what are the register file outputs?
two 32 bit data values that were read from the read registers
what is the control component of the register file?
RegWrite
1 bit indicating whether the write register should be written to
what is the ALU input?
two 32 bit operands
what are the ALU outputs?
one 32 bit result computed
one 1 bit signal indicating whether the result was zero
what is the ALU control?
a multi bit signal selecting which of the supported operations the ALU will perform on the operands
what is the ALU control?
a multi bit signal selecting which of the supported operations the ALU will perform on the operands
Control unit input?
6 bit opcode
Control unit output?
currently unknown number of 1 bit signals to other elements
Control unit output?
currently unknown number of 1 bit signals to other elements
Why do we need 16-32 bit sign extenders?
hardware adders require their operands to be the same width so the immediate operand needs to be larger than 16 bits
Why do we need shifters?
We need to shift left 2 because when executing beq, the offset used to calculate the target address has to be multiplied by 4, equivalent to a left shift of 2
what does ALU do for each type of instruction?
R - report result of operation
I - report address to be read from/written to
J - report comparison of registers and branch target address
how is the address set for the next instruction fetch?
PC + 4 (for R/I type)
OR branch target
OR jump target
what does PC do?
store address of next instruction to be fetched, sends it to the interface for the instruction
Why does PC get incremented by 4?
to move on to the next instruction
where in the memory is rs?
25:21
where in the memory is rt?
20:16
where in the memory is rd?
15:11
where in the memory is op?
31:26
where in the memory is funct?
15:0
what does control do for R-format instructions?
tell ALU control to use the funct bits and sets RegWrite to 1
what does ALU control do for R-format instructions?
sets ALU to the correct operation
what does control do for load instructions?
tell ALU control to add operands and sets RegWrite to 1
Why do multiplexors exist in the MIPS architecture?
They prevent conflicts with the write location and the data sent to the ALU
RegDst
selects the write register number (rd for load or rt for R) dont care for store
ALUSrc
selects operand for ALU (either register 2’s value for R type or extended immediate for load/store)
MemtoReg
selects write data for register file (either computed result from ALU for R or data read from address for load)
