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CS 2505/2506 > 2506 Midterm Review > Flashcards

2506 Midterm Review Flashcards

1
Q

format for R-type instruction

A

op rs rt rd shamt funct

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2
Q

format for I-type load/store instruction

A

op rs rt 16-bit imm

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3
Q

format for J-type branch instruction

A

op 26-bit imm

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4
Q

rt register

A

2nd source register

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5
Q

rs register

A

1st source register

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6
Q

rd register

A

destination register

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7
Q

load command specifies destination

A

first

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8
Q

store command specifies destination

A

last

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9
Q

beq

A

branch on equal

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10
Q

bne

A

branch on not equal

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11
Q

instructions that take 2 registers

A

addi
lw
beq

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12
Q

instructions that take only an immediate

A

j

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13
Q

instructions that take 3 registers

A

add, or

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14
Q

how long are MIPS instructions

A

32 bits

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15
Q

shamt

A

shift amount

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16
Q

for an I-type instruction, where is content written?

A

in $rt

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17
Q

how is the appropriate address calculated from an I-type instruction?

A

the contents of $rs is fetched to the ALU and added to the immediate field

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18
Q

how many bits is an opcode?

A

6 bits

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19
Q

what does a memory unit do?

A

store instructions and data values

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20
Q

what does a register do?

A

store instructions and data values within the processor

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21
Q

what does an ALU do?

A

implement basic operations

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22
Q

what do multiplexors do?

A

allow selection among different choices for operands and data values

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23
Q

what does a control unit do?

A

decode instructions and manage other elements during execution

24
Q

what does a sign extension unit do?

A

widen values from 16 to 32 bits

25
Q

what does a shift unit do?

A

perform multiplication by a power of 2

26
Q

What inputs does a memory unit take?

A

a 32 bit address that will be accessed

a 32 bit data value to be written to that address (when memwrite is on)

27
Q

What is the output of a memory unit

A

32 bit value that was read from the given address

28
Q

what are the 2 controls within a memory unit?

A

MemWrite
MemRead
Both contain a single bit and indicate whether or not the address should be written to or read from

29
Q

where are registers organized in the MIPS architecture?

A

a register file

30
Q

what are the register file inputs?

A

two 5 bit numbers specifying the two registers to be read from
one 5 bit register number to be written to
32 bit data value to be written into the target register

31
Q

what are the register file outputs?

A

two 32 bit data values that were read from the read registers

32
Q

what is the control component of the register file?

A

RegWrite

1 bit indicating whether the write register should be written to

33
Q

what is the ALU input?

A

two 32 bit operands

34
Q

what are the ALU outputs?

A

one 32 bit result computed

one 1 bit signal indicating whether the result was zero

35
Q

what is the ALU control?

A

a multi bit signal selecting which of the supported operations the ALU will perform on the operands

36
Q

what is the ALU control?

A

a multi bit signal selecting which of the supported operations the ALU will perform on the operands

37
Q

Control unit input?

A

6 bit opcode

38
Q

Control unit output?

A

currently unknown number of 1 bit signals to other elements

39
Q

Control unit output?

A

currently unknown number of 1 bit signals to other elements

40
Q

Why do we need 16-32 bit sign extenders?

A

hardware adders require their operands to be the same width so the immediate operand needs to be larger than 16 bits

41
Q

Why do we need shifters?

A

We need to shift left 2 because when executing beq, the offset used to calculate the target address has to be multiplied by 4, equivalent to a left shift of 2

42
Q

what does ALU do for each type of instruction?

A

R - report result of operation
I - report address to be read from/written to
J - report comparison of registers and branch target address

43
Q

how is the address set for the next instruction fetch?

A

PC + 4 (for R/I type)
OR branch target
OR jump target

44
Q

what does PC do?

A

store address of next instruction to be fetched, sends it to the interface for the instruction

45
Q

Why does PC get incremented by 4?

A

to move on to the next instruction

46
Q

where in the memory is rs?

A

25:21

47
Q

where in the memory is rt?

A

20:16

48
Q

where in the memory is rd?

A

15:11

49
Q

where in the memory is op?

A

31:26

50
Q

where in the memory is funct?

A

15:0

51
Q

what does control do for R-format instructions?

A

tell ALU control to use the funct bits and sets RegWrite to 1

52
Q

what does ALU control do for R-format instructions?

A

sets ALU to the correct operation

53
Q

what does control do for load instructions?

A

tell ALU control to add operands and sets RegWrite to 1

54
Q

Why do multiplexors exist in the MIPS architecture?

A

They prevent conflicts with the write location and the data sent to the ALU

55
Q

RegDst

A

selects the write register number (rd for load or rt for R) dont care for store

56
Q

ALUSrc

A

selects operand for ALU (either register 2’s value for R type or extended immediate for load/store)

57
Q

MemtoReg

A

selects write data for register file (either computed result from ALU for R or data read from address for load)

CS 2505/2506 (3 decks)

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