2 - x86 Processor Architecture

Question 1

What does the CPU do and have?

Answer 1

It is where calculations and logical operations take place. It has:

1. Limited number of storage locations (registers)
2. Clock to synchronize internal CPU operations with system
3. Control Unit (CU) to coordinate sequence of steps when executing instructions
4. Arithmetic Logic Unit (ALU) to perform arithmetic (add, subtracting) and logic operations (AND, OR, NOT).

Question 2

How is the CPU attached to the rest of the computer?

Answer 2

The CPU is attached to the CPU socket in the computer’s motherboard. Most pins connect to the data bus, the control bus, and the address bus, all of which connect to everything else.

Question 3

What is the memory storage unit?

Answer 3

Where instructions and data are held while a computer program is running. The storage unit receives requests for data from the CPU, transfers data from RAM to the CPU (to process all data), and transfers data from the CPU into memory.

Question 4

What is a “bus”?

Answer 4

A group of parallel wires that transfer data from one part of the computer to another.

1. Data bus transfers instructions and data between CPU and memory.
2. I/O bus transfers data between CPU and system input/output devices.
3. Control bus uses binary signals to synchronize actions of all devices attached to system bus.
4. Address bus holds the addresses of instructions and data when the currently executing instruction transfers data between the CPU and memory.

Question 5

What is a “machine cycle” or “clock cycle”?

Answer 5

The time required for one complete clock pulse (usually 1 billion ties per second).

Most machine require between 1-50 clocks. However, instructions needing memory access have empty clock cycles (wait states) because of the different speeds of the CPU, system bus, and memory circuits.

Question 6

What are the steps of an instruction execution cycle?

Answer 6

1. Fetch: the CPU has to fetch the instruction from an area of memory called the instruction queue.
2. Decode: The CPU looks at the binary bit pattern. If operands are involved, the CPU fetches the operands from registers and memory (sometimes including address calculations).
3. Execute: Executes the instruction, and if an output operand was part of the instruction, the CPU stores the result in the operand.

Question 7

What is an operand?

Answer 7

A value that is either an input or an output to an operation.

For example, Z = X + Y has two input operators (X and Y) and a single output operand (Z).

Question 8

What is the data flow within the typical CPU during the instruction execution cycle?

Answer 8

First, to read program instructions from memory, an address is placed on the address bus.

Next, the memory controller places the requested code on the data bus, making the code available in the code cache.

The instruction pointer’s value determines which instruction will be executed next, and the instruction is analyzed by the instruction decoder, causing digital signals to be sent to the control unit, which coordinates the ALU and floating-point unit.

Question 9

What are the steps required to read from memory?

Answer 9

1. Place the address of the value you want on the address bus
2. Assert (change the value of) the processor’s RD (read) pin.
3. Wait one clock cycle for the memory chips to respond.
4. Copy the data from the data bus into the destination operand.

Question 10

How does the cache speed up a computer?

Answer 10

The most recently used instructions and data are stored in high-speed memory (cache).

Also, when the CPU begins to execute a program, it can look ahead and load the next thousand instructions on the assumption that these instructions will be needed fairly soon.

Question 11

What is a cache hit/miss?

Answer 11

A cache hit is if the processor is able to find its data in cache memory.

A cache miss is if the CPU tries to find something in cache and it’s not there.

Question 12

What are the two types of cache memory in the x86 family?

Answer 12

Level-1 cache (primary cache) is stored right on the CPU.

Level-2 cache (secondary cache) is a little bit slower, and attached to the CPU by a high-speed data bus.

Question 13

Why is cache memory faster than conventional RAM?

Answer 13

Cache memory is constructed from a special type of memory chip (static RAM) that is expensive, but does not have to be constantly refreshed to keep its contents.

Conventional RAM (dynamic RAM), must be refreshed constantly.

Question 14

How is a program loaded and executed?

Answer 14

Before the program can run, it must be loaded into memory by a utility known as a program loader.

After loading, the operating system must point the CPU to the program’s entry point (the address at which the program is to begin execution).

Question 15

Which two additional steps are required in the instruction execution cycle when a memory operand is used?

Answer 15

Fetch memory operands and store memory operands.

Question 16

What are the three primary modes of operation of x86 processors?

Answer 16

1. Protected mode (a sub mode of this is virtual-8086).
2. Real-address mode
3. System management mode

Question 17

What is the protected mode?

Answer 17

The native state of the process, in which all instructions and features are available.

Programs are given separate memory areas called segments, and the processor prevents programs from referencing memory outside their assigned segments.

Question 18

What is the virtual 8086 mode?

Answer 18

While in protected mode, the processor can directly execute real-address software like MS-DOS programs in a safe environment. That way, if a program crashes or attempts to write data into the system memory area, it will not affect other programs at the same time. Today, you can execute separate virtual 8086 sessions at the same time.

Question 19

What is the real-address mode?

Answer 19

Real-address mode implements the programming environment of an early Intel processor with a few extra features (like the ability to switch into other modes). This is useful if a program needs direct access to system memory and hardware devices.

Question 20

What is system management mode?

Answer 20

SMM provides an operating system with a mechanism for implementing functions like power management and system security. These are usually implemented by computer manufacturers who customize the processor for a particular system setup.

Question 21

How much address space is there in a 32-bit environment?

Answer 21

In 32-bit protected mode, a task or program can address a linear space up to 4GB. Then, with extended physical addressing, a total of 64 GB could be addressed.

However, real-address mode programs can only address a range of 1 MB. Additionally, if the processor is in protected mode and running multiple programs in virtual 8086 mode, each program has its own 1MB memory area.

Question 22

What are the basic program execution registers?

Answer 22

1. Eight 32-bit general purpose registers.
2. Six 16-bit segment registers.
3. An EFLAGS register (processor status flags).
4. An EIP register (instruction pointer).

Question 23

What are the general purpose registers?

Answer 23

They are mostly for arithmetic and data movement.

Four of them (EAX, EBX, ECX, and EDX) can be addressed as 16-bit or 8-bit values. For example, the 16-bit of EAX is AX (the second half). The 8-bit ones are AH (high) and AL (low).

The others can ONLY be accessed by their 32-bit (ESI, EDI, EBP, ESP) or 16-bit names (SI, DI, BP, SP).

Question 24

What specialized uses do some general purpose registers have?

Answer 24

1. EAX (extended accumulator register) - automatically used by multiplication and division instructions.
2. ECX automatically used as a loop counter by CPU.
3. ESP (extended stack pointer) addresses data on the stack.
4. ESI (extended source index) and EDI (extended destination) are used by high speed memory transfer instructions.
5. EBP (extended frame pointer register) is used by high-level languages to reference function parameters and local variables on the stack.

Question 25

What are segment registers?

Answer 25

In real-address mode, 16-bit segment registers indicate base addresses of preassigned memory areas named segments.

In protected mode, these hold pointers to segment descriptor tables. Some segments hold program instructions, others hold variables, and another is the stack segment.

Question 26

What is the instruction pointer?

Answer 26

The EIP register contains the address of the next instruction to be executed. Certain machine instruction manipulate EIP so the program branches to a new location.

Question 27

What is the EFLAGS register?

Answer 27

Individual binary bits that control the operation of the CPU or reflect the outcome of some CPU operation.

A flag is set when it equals 1 and clear when it equals 0.

Question 28

What are control flags?

Answer 28

Control flags control the CPU’s operation. For example, they can cause the CPU to break after every instruction executes, interrupt when arithmetic overflow is detected, enter virtual 8086 mode, and enter protected mode.

Question 29

What are status flags?

Answer 29

These reflect the outcome of arithmetic and logical operations performed by the CPU, including overflow, sign, zero, auxiliary carry, parity, and carry flags.

Question 30

When are the carry flag (CF), overflow flag (OF), and sign flag (SF) set?

Answer 30

CF: when the result of an unsigned arithmetic operation is too large to fit into the destination.

OF: when the result of a signed arithmetic operation is too large or too small to fit into the destination.

SF: when the result of an arithmetic or logical operation generations a negative result.

Question 31

When are the zero (ZF), auxiliary carry (AC), and parity (PF) flag set?

Answer 31

ZF: when the result of an arithmetic or logical operations generates a result of zero.

AC: when an arithmetic operation causes a carry from bit 3 to bit 4 into an 8-bit operand.

PF: set if the least-significant byte in the result contains an even number of 1 bits. Otherwise PF is clear. In general, it is used for error checking if data might have been altered or corrupted.

Question 32

What are MMX registers?

Answer 32

These support special instructions SIMD (single-instruction, multiple data).

Although these appear to be separate registers, their names are aliases to the same registers used by the floating point unit.

Question 33

What are XMM registers?

Answer 33

The eight 128-bit regisers that are used by streaming SIMD extensions to the instruction set.

In contrast to MMX registers, these are not the same as the floating point unit.

Question 34

What is the floating point unit?

Answer 34

It is integrated into the main processor chip. There are 8 floating-point data registers named ST(0) to ST(7), as well as control registers and pointer registers.

Question 35

How is the 64-bit x86 processor different from the 32-bit?

Answer 35

1. Addresses are 64 bits long, allowing for a virtual address space of 2^64 bytes (although currently only the lowest 48 are used)
2. It can use 64-bit general-purpose registers, allowing instructions to have 64-bit integer operands.
3. It uses 8 more general purpose registers than the x86.
4. It uses a 48-bit physical address space, which supports up to 256 terabytes of RAM.

Question 36

What are the two 64-bit operation modes?

Answer 36

Compatibility mode: existing 16-bit and 32-bit applications can run without being recompiled (but not on 64-bit Windows).

64-Bit mode: processor runs applications that use the 64-bit linear address space, which is the native mode for 64-bit Windows.

Question 37

How are the 64-bit processor registers different?

Answer 37

1. Sixteen 64-bit general purpose registers (as opposed to 8).
2. Eight 80-bit floating point registers.
3. A 64-bit status flags register (RFLAGS), but only the lower 32 bits are used.
4. A 64-bit instruction pointer named RIP.
5. Eight 64-bit MMX registers.
6. Sixteen 128-bit XMM registers ( as opposed to 8).

Question 38

How are the general purpose registers different in 64-bit mode?

Answer 38

In 64-bit mode, the default operand size is 32 bits. By adding the REX prefix to each instruction, the operands can be 64 bits long, opening up 16 general-purpose registers.

All the same registers as in 32-bit mode, PLUS eight numbered registers, R8 through R15.

Question 39

How does 64-bit mode impact high and low byte access?

Answer 39

A single instruction cannot access both a high-byte register (AH, BH, CH, and DH) and at the same time, the low byte of one of the new byte registers (like DIL).

Question 40

How does 64-bit mode impact the flags register?

Answer 40

The 32-bit EFLAGS register is replaced by the 64-bit RFLAGS register. They share the same lower 32 bits, and the upper 32 bits of RFLAGS are not used.

However, the status flags are the same in 32-bit mode and 64-bit mode.