1P3 Digital Circuits Flashcards
How do you solve a circuit for a digital gate?
Plot the characteristic of the bottom item first, and plot the mirror of the top item starting from the supply voltage.
How do you work out the inverter characterstic for a resistor - NMOS combo?
By plotting resistor characterstics on top of the transistor one, and esting the Vds for different values of Vgs.
How are NOR circuits designed?
two transistors in parallele.
How are NAND circuits designed?
two transistors in series.
What limits the speed in NMOS logic?
the parasitic capacitance between the output voltage and the ground. Can take up to 30ns.
How can transistors behave like resistors?
By connecting the gate to the drain so Vds = Vgs.
Leads to a resistance of around 900 ohms
Advantages of using FET as a resistor?
Much smaller on the chip
When is power consumed in a resistor NMOS combo?
When Vin is high, there will be a current on the order of 10mA, large power dissapation.
What is a CMOS inverter?
PMOS and NMOS in series. With drain adjacent to drain. Vin connected to the gate of both.
List the advantages of CMOS logic.
Much better inverter characteristic closer to ideal, almost vertical at 5V.
Due to the nature of intersecting, charactersitics.
Much lower power dissapation, Only dissapated whilst the device is changing state.
Low propogation delay (8 - 50ns)
A + (A.C) =
A
A.(A+C)=
A
A + (B.C…) =
(A+B).(A+C)…
A.(B+notB)=
A
What is the quickest way to find an expression for Y in terms of sum of products? (Boolean algebra)
Write down an expression for Y directly
What is the quickest way to find an expression for Y in terms of product of sums?
find an expression for notY and use demorgans
How to work out a circuit purely using NAND gates?
Write down the Karnaugh map and find the sum-of-products, the use De Morgan to convert this to a NAND based expression.
How to work out a circuit purely using NOR gates?
Write donw simplest sum of products for the inverse of the ouput, use De Morgan to convert.
How do you make a 5 variable Karnaugh map?
Place two 4 variable Karnaugh maps next to one another.
What is a static 1 hazard.
When propogation delays of the logic gates result in in the output switching from 1 to 0 and then back to 1 due to a single change in input.
What is static zero hazard.
When propogation delays of the logic gates result in in the output switching from 0 to 1 and then back to 0 due to a single change in input.
How do you fix a static 1-hazard?
Drawing a Karnaugh map of the ouput and making sure all of the sums of products overlap.
How do you fix a static 0-hazard?
Drawing a Karnaugh map of all the inverse of the ouputs, making sure all of the sums of products overlap.
What is a dynamic hazard?
When a signal changes more than once when it’s supposed just to change once.
What is unit distance codes?
Where only one bit changes at time.
For an 8 bit signed number, what set of numbers represents positive, and what set represents negative (in hex)?
Positive 00 - 7F
Negative 80 - FF
Convert a positive number to a negative number how?
invert all the bits then add 1.
When does 2’s complement overflow?
When the carry into MSB is not equal to the carry out of MSB.
Deliberately ignoring carry out into MSB.
What is Binary Coded Decimal?
When each digit of the decimal number is stored as one 4 bit segment.
How many bits are used for Alphanumeric character codes?
7 bits, first 32 are control codes, rest are upper, lower case letters, numbers and punctuation.
8 bits for an extraa 128 graphics characters.
What is parity?
A form of error detection, sets a particular bit to ensure an even number of bits are always on. Can reject if there are an odd number of bits.
Can only detect 1 bit errors.
What is an S-R bistable?
A set reset bistable, simplest form.
Works except for the case S=R=1.
Q1 = S + not (Q2) = not(not(s).Q2)
Q2 = R + not(Q1) = not(not(R).Q1)
How does a gated SR bistable work?
Can only change state when the gate input is high.
How does a master-slave gated s-r bistable work?
What is its symbol?
First bistable changes on the clock goes low, sensitive to the S-R inputs.
Second bistable changes on the rising edge of the next clock.
Output of second bistable is Q and not(Q)
s-r with a clock with a triangle.
What are input and clear reffered to as?
asynchronous inputs.
How does preset and clear work?
They are active low signals.
If preset goes low, the output goes high.
If clear goes low, the output goes low.
They are connected the NAND of the slave bistable.
What is a D-type latch?
S = D
R = notD
for a master slave S-R bistable
What is the difference between SR and JK?
J is anded with not(Q) before it goes to S.
i.e. S = J.not(Q)
R = K.Q
This prevents S=R=1. If J=K=1 this input triggers the ouput to toggle.
How do you create a divide by 2 counter?
1 JK bistable where both J=K=1.
How does a ripple counter work?
all J-K = 1, output of one is connected to the next.
How does a shift register work?
A series of D type latches with outputs connected to the next input.
How does parallel loading work?
A series of inputs connected via NAND gates and invertes to preset and clear. With a load wire which is set to one to load the numbers.
It is also a shift register so once the load is set to zerothe numbers can cycle out,
What is a serial data link?
A parallel loading shift register followed by a single wire and then a shift register. Allows data to be transmitted with only one wire despite having many bits.
What is a Johnson counter?
A shift register with the output connected via an inverter to the input. (or other logic functions).
Of length N generates a sequence of length 2N.
How can divide by N counters be made where N is not a power of 2?
the clear function connected to the appropriate logic gates and the bistable outputs.
What are the 5 stages to synchronous logic design?
State diagram, bistable allocation, state transition table, Karnaugh maps, circuit diagram.
What are the two types of DAC?
Weighted resistor DAC, lots of different sizes of resistors. D type latches and a transimpedance amplifier.
R-2R Ladder DAC
switches for all the inputs. R resistors accross the top and 2R down the branches. Each current is 2x the previous.
Also connected to a transimpedance amplifier.
How does hysteresis work?
FOr the comparator to trigger, the input voltage has to exceed the upper bound to change state, and go below the lower bound to change state again.
How does a flash ADC work?
A long potential divider used as many different Vref. Used to be a ladder.
Need 8 bits to convert 8 levels, ineffecient.
How many comparators does a n bit ADC need?
2^n-1
REQUIRES LOADDDSSS takes up laods of space
Impossible for high resolution such as 16bit
stair-step ramp method for ADC.
A divide by n counter (ramping up) is connected to a DAC which is connected with 1 comparator to an analogue input. Control logic is used to assign a digital value to this.
SLOW but few comparators.
What are the inputs and outputs to an adder circuit?
Ai, Bi (two bits to be added), Ci (carry)
Output:
Ci+1 (carry to next bit), Si (result for that bit.
Can be stacked together.
WHat is an ALU?
An arithmetic logic unit.
Takes in n bit inputs a and b (could be single bits or entire words).
Uses function code + carryin
Completes operation (add, subtract, and, or)
produces an outpu and carry out
What buses are bidirectional and which ones are unidirectional?
Data bus is bidirectional (read/write)
Address and control bus are unidirectional.
What steps are needed to read data from memory?
Set address on the address bus,
set read/write wire of control bus to high
set address vlid control wire high.
This activates chip select (active low signal), memory location is placed on data bus.
What steps are needed to write to memory?
Set address on address bus
Set read/write wire to low
Set address valid control wire high.
Activiates the chip select. Contents of the data bus placed at memory location.
Where is the input/output register on the PIC?
GPIO (bidirectional, apart from pin 3 which is always an input) pins 0-5
How does the program counter work?
Total of 13 bits split over two memory locations. PCL and PCLATH.
Stores the program memory address for the next instruction to be executed.
Where is the direction of the GPIO set?
On the TRISIO register.
What is the fetch-decode-execute cycle?
Fetch the instruction from the address stored in the program counter.
Then decoded by the microprocessor.
Once decoded it is executed and the program counter is incremented so it contains the address of the next instruction.
What does d specify in op codes.
The location of the destination. F (d=1), W(d=0)
What does the word select line inside RAM do?
It selects an individual word to either read or write to.
What does write enable to?
Enables the output of the S-R bistable to be modified.
How does the data interface at the edge of the chip work?
Read write and chip select wire either enables the data out tri-state buffer, or enables the write enable wire enabling the S-R bistables to be edited.
How do tri-state buffers work.
If E (enable) is 1 then the output matches the input, if E is 0 then the output is floating.
How does the not(CS) wire work?
It takes the signal from the first N of the address wires (starting from the MSB) and uses logic functions to assign each chip.
What is memory mapped input/output?
When read or not(write) is selected can decide whether the input is written to the data bus or the data bus is written to the output port.,
What is the difference between SRAM and DRAM?
SRAM is static RAM which is simple, with good storage density , speeedy access, and low power consumption. Used for cache memories on motherboards.
DRAM is dynamic RAM. Has a very complex interface because it must have its contents refreshed continuously (forgets in milliseconds), consumes power even when not in use, slower than SRAM, very dense storage, used as main RAM for PC.
What are other types of memory? (excluding RAMs)
ROM - Read only memory, set at manufacture, microprocessor cannot change.
EPROM - erasable programmable read only memory, can be programmed using higher voltage than microprocessor, can be erased using a UV light
FLASH memory - non volatile storage that can be electrically erased and reprogrammed.
How do you extract a series of bits and the rest zeros from a word?
Using andwf with 1s set for the bits you want.
After rlf what does c flag tell you?
Whether the number was positive or negative (if it was 2’s complement)
What are the nibbles of a word?
bits 0-3 lower nibble
bits 4-7 upper nibble
What is the digit carry flag?
Set if operation causes carry from bit 3
What is the zero flag?
Set if the result of an operation is zero.
What needs to be noted for adding two sixteen bit numbers?
Make sure you have considered whether the carry bit is 1 and increment one of the upper 8 bit numbers before final addition.
What are boxes and diamonds used for in flow charts?
Boxes - actions
Diamonds - tests
When does an operation take two clock cycles?
Operations affecting PC counter contents. goto call return
test branch instructions, operates a nop if the skip aspect is triggered.
How does the FSR work?
the address is loaded into FSR.
Referencing INDF, refences the location reffered to by FSR
How does the stack work?
Pushing adds a piece of data onto the top of the stack.
Popping removes a piece of data from the top of the stack.
Last in First out
When is the stack used on the PIC microprocessor?
PC is pushed onto the stack when a subroutine is execute. So the program can go back to it.
Stack is popped when it returns
What is a subroutine?
Discreete programme function can be jumped to using call.
What happens when the reset pin is set to low?
The program counter is reinitialized to 0x0000
How does the reset pin work?
In parallel with a capacitor which increases from 0V after the reset button is presed such that the micro-processor can restart in suitable time.
