17-22 Flashcards
CPU is attached to the main memory of the system via a __.
Some devices are connected to the system via a __.
memory bus;
general I/O bus
I/O Architecture:
Buses
Data paths provided to enable information between CPU(s), RAM, and I/O devices
I/O bus:
(2)…
• Data path that connects a CPU to an I/O device
• I/O bus is connected to I/O device by three hardware components:
- I/O ports
- Interfaces
- Device controllers
Canonical Devices have two important components:
(2)…
- Hardware interface allows the system software to control its operation
- Internals which is implementation specific
Canonical Device:
Registers:
(3)…
By reading and writing these registers, the OS can control device behavior
1. status register
• See the current status of the device
2. command register
• Tell the device to perform a certain task
3. data register
• Pass data to the device, or get data from the device
The Canonical Protocol:
Example of programmed I/O (PIO):
CPU is involved with the __.
data
movement
The Canonical Protocol:
Operating system waits until…
• Simple and correct
• Wastes CPU time just waiting for the device
- Switching to another ready process would utilize the CPU more
Interrupts:
(2)…
• Put the I/O request process to sleep and context switch to another
• When the device is finished, wake the process waiting for the I/O by interrupt
- Allows for the CPU and the disk to be properly utilized
Polling vs. interrupts:
(3)…
- Interrupts are not always the best solution
• If a device performs very quickly interrupts slow down the system
- Context switches are expensive - If a device is fast, polling is preferred
- If the device is slow, interrupts are better
More efficient data movement with DMA (Direct Memory Access)
CPU wastes a lot of time to copy a large chunk of data from memory to the device
• Copy one word at a time to the device
• After data is copied then it can be written to disk
Device interaction:
Two main ways to communicate with devices:
(2)…
- I/O instructions: a way for the OS to send data to specific device registers
- Memory-mapped I/O
Device interaction:
- I/O instructions: a way for the OS to send data to specific device registers
(2) … - Memory-mapped I/O
(3) …
- • E.g., in and out instructions on x86
• Typically a privileged instruction – why? - • Device registers available as if they were memory locations
• The OS loads (to read) or stores (to write) to the device instead of main memory
• No new instructions, same as a memory read or write
The OS interface: the device driver:
Abstraction encapsulates any specifics of device interaction:
(3)…
- At the lowest level, the OS must know how the hardware works
- We call this software a device driver
- Provides a higher-level interface to the rest of the system
Example Driver: File system Abstraction
(3)…
• Application is unaware of the type of file system
• File system is unaware of which type of disk it is using
- Issues block read/write requests to a generic block layer
• Many drivers expose a raw interface to allow for special applications
Problems With Device Driver Abstraction:
• If there is a device with special capabilities, these capabilities will go unused in the __.
generic interface layer
Basic IDE Protocol:
(6)…
- Wait for drive to be ready
• Read Status Register (0x1F7) until drive is not busy and READY - Write parameters to command registers
• Write the sector count, logical block address (LBA) of the sectors to be accessed, and drive number to command registers (0x1F2-0x1F6) - Start the I/O
• Write the READ/WRITE command to command register (0x1F7) - Data transfer (for writes)
• Wait until drive status is READY and DRQ (drive request for data)
• Write data to data port - Handle interrupts
• In the simplest case, handle an interrupt for each sector transferred
• DMA allows for batching and a final interrupt when the entire transfer is complete - Error handling
• After each operation, read the status register
• If the ERROR bit is on, read the error register for details
Basic IDE Protocol:
Wait for drive to be ready
(1)…
• Read Status Register (0x1F7) until drive is not busy and READY
Basic IDE Protocol:
Write parameters to command registers
(1)…
• Write the sector count, logical block address (LBA) of the sectors to be accessed, and drive number to command registers (0x1F2-0x1F6)
Basic IDE Protocol:
Start the I/O
• Write the READ/WRITE command to command register (0x1F7)
Basic IDE Protocol:
Data transfer (for writes)
(2)…
- Wait until drive status is READY and DRQ (drive request for data)
- Write data to data port
Basic IDE Protocol:
Handle interrupts
(2)…
- In the simplest case, handle an interrupt for each sector transferred
- DMA allows for batching and a final interrupt when the entire transfer is complete
Basic IDE Protocol:
Error handling
- After each operation, read the status register
* If the ERROR bit is on, read the error register for details
I/O Summary:
For efficiency we use:
(2)…
- Interrupts: allow process to sleep while slow I/O takes place
- DMA: Allow transfer between memory and a device with little CPU intervention