1.1.1.Characteristics of contemporary processors (chp 1)

Question 1

Arithmetic Logic Unit (ALU)

Answer 1

The ALU completes all of the arithmetical and logical operations. Including all math operations i.e. addition, subtraction with floating numbers.
Logic operations include boolean logic operations such as AND OR NOT.

Question 2

The Control Unit (CU)

Answer 2

• Controls and coordinates the activities of the CPU
• Manages the flow of data between the CPU and other devices
• Accepting the next instruction
• Decoding instructions

Question 3

Registers

Answer 3

Small memory cells that operate at a very high speed. They’re used to temporarily store data and all arithmetic, logical and shift operations occur in these registers.

Question 4

Program Counter (PC)

Answer 4

holds the address of the next instruction to be executed.

Question 5

Accumulator (ACC)

Answer 5

stores results from calculations performed by the ALU

Question 6

Memory Address Register (MAR)

Answer 6

holds address of a location that is to be read from or written to.

Question 7

Memory Data Register (MDR)

Answer 7

temporarily stores data that has been read or data that needs to be written.

Question 8

Current Instruction Register (CIR)

Answer 8

holds the current instruction being executed , divided up into operand and opcode.

Question 9

Buses

Answer 9

• set of parallel wires which connects two or more components inside the CPU.
• width of the bus is the no. of parallel wires that bus has
• width is proportional to the no. of bits that can be transferred simultaneously at any given time.

Question 10

Address Bus

Answer 10

• used to transmit the memory addresses specifying where data is to be sent to or retrieved from.
• the width of the address bus is proportional to the number of addressable memory locations.

Question 11

Data Bus

Answer 11

• bi-directional bus

- used for transporting data and instructions between components.

Question 12

Control Bus

Answer 12

• bi-directional bus used to transmit control signals between internal and external components.
• it coordinates the use of the address and data buses and provide status info between system components.
• sends control signals.

Question 13

Assembly Language

Answer 13

• low level language that is next level up from machine code. It uses mnemonics to represent machine code, making it easier to remember and use.
• commands from assembly language are processor specific
• one to one relationship with specific assembler.

Question 14

LDA

Answer 14

means to load the value in a memory location into the accumulator.

Question 15

STA

Answer 15

means to store the value in the accumulator into a given memory location.

Question 16

Fetch- decode - execute cycle.

Answer 16

Fetch:
1. PC copies address of next instruction to MAR
2.MAR places address of the next instruction on address bus
3.CU triggers a read signal that causes RAM to place the instruction being asked for on the data bus.
4.The instruction on data bus is loaded into the MDR.
5.MDR copies the instruction to CIR.
Decode:
6.CPU examines instruction in CIR and decodes it using decode unit - issues a series of micro-instructions
Execute:
7.The instruction within the CIR is executed by CPU (execute unit)
Reset:
8.Now that the CPU is executing an instruction, the program counter can be reset to point to the next instruction.

Question 17

Pipelining

Answer 17

The process of completing the fetch-decode-execute cycles of three separate instructions simultaneously. While one instruction is being executed, another can be decoded and another fetched.
-reduces the amount of the CPU that is kept idle.

Question 18

Clock speed (how it affects performance)

Answer 18

• Clock speed is the time taken for one FDE cycle to complete.
• Greater the clock speed, the more calculations can be carried out per second and therefore the greater the clock cycle

Question 19

No. of cores (how it affects performance)

Answer 19

• A core is an independent processor that is able to run its own FDE cycle.
• Not necessarily speeding it up, it just allows you to carry out more instructions at the same time.
• not all programs are able to utilise multiple cores efficiently as they are not designed to do so.

Question 20

Amount of Cache (its affect on CPU performance)

Answer 20

-instructions from main memory are copied to cache so if required, they can be accessed quicker. As cache fills up, unused instructions are replaced.

Question 21

What is the Von Neumann Architecture

Answer 21

-includes the basic components of the computer and processor in which a shared memory and shared data bus is used for both data and instructions.

Question 22

What is the Harvard Architecture

Answer 22

• it has physically separate memories and buses for instructions and data, more commonly used with embedded processors.
• This is useful for when memories have different characteristics i.e. only red.

Question 23

Advantages of Von Neumann Architecture

Answer 23

• cheaper to develop as the control unit is easier to design
• programs can be optimised in size
• it follows the FDE

Question 24

Advantages of Harvard Architecture

Answer 24

• quicker execution as data and instructions can be fetched in parallel
• memories can be of different sizes, which can make more efficient use of space.
• pipelining (+explanation)

Question 25

Contemporary processing

Answer 25

-contemporary processors use a combination of Harvard and Von Neumann architecture. Von Neumann is used when working with data and instructions in main memory, but uses Harvard architecture to divide the cache into instruction cache and data cache.