1.1.1 Structure Of The Processor Flashcards
What is Moore’s law?
The number of transistors on a processor will double every two years.
What does the CU do?
Sends out control signals to other parts of the CPU.
Fetches instructions from memory, decodes them and then executes them.
Contains the clock.
What does the ALU do?
Performs arithmetic.
Performs logical operations (AND, NOT, OR etc.)
Performs logical comparisons like greater than.
What are the 5 specific registers?
PC, CIR, MAR, MDR, ACC.
What does the PC do?
It hold the location of the next instruction.
Jump instructions are when the flow of control is altered.
What is the MAR?
It stores the address in memory of the data that is to be fetched from or sent to memory.
What is the MDR?
Stores the data that has been fetched from or is about to be stored in memory.
What is the CIR?
Stores the most recently fetched instruction, waiting to be decoded and executed.
What is the ACC?
It Holds the results of calculations and operations performed by the ALU.
What are the 3 buses?
Address Bus, Data Bus and Control Bus.
What is the Address Bus?
It provides a memory address to the system memory or input/output devices.
What is the Data Bus?
It transfers data between the CPU and memory or input/output devices and vice verse.
What is the Control Bus?
It provides control signals that cause the memory or input/output devices to perform a read or write operation.
Describe the Fetch sequence (hahaha)!
1: The PC copies the address of the next instruction it contains into the MAR.
2: The CU loads the address to be used onto the address bus.
3: The CU sends a read signal down the control bus that causes RAM to place the instruction being asked for onto the data bus.
4: The instruction on the data bus is loaded onto the MDR.
5: The MDR copies the instruction into the CIR.
6: The PC can now be incremented by one to point to the next instruction.
Describe the Decode sequence?
The CU examines the instruction in the CIR and decodes it. (Every CPU has an instruction set that defines what the decoder understands.)
Describe the Execute stage?
The instruction in the CIR is carried out by the CPU.
This process may use the ACC, the CLU as well as taking data values from memory.
Then Repeat the Process!
What are the 3 key factors affecting CPU performance?
1: Clock Speed
2: Cache Memory
3: Multiple Cores
(maybe pipelining)
((as well as GPU, RAM and secondary storage))
Pipelining Definition?
The technique of fetching an instruction while the prior one is being decoded and the one before is being executed.
What are the issues with pipelining?
Sometimes programs branch and the program will have to predict this. If the controller makes a mistake, the pipelines will have to be emptied (flushed) which will degrade performance.
What actually is the VON Neumann Architecture?
Something that stores program instructions and data together in the same memory unit.
What are the key features of VNA?
1: Shared memory space for instructions and data.
2: Data stored in binary.
3: Single CU.
4: Single ALU.
5: Follows a linear FDE cycle.
6: Processes instructions sequentially.
7: Registers are used for fast access to data and instructions.
What is the VN Bottleneck?
When the CPU runs much faster than the transfer speed of the data bus which could lead to the CPU waiting for data and instructions to arrive. (A solution could be cache memory.)
What is contemporary processor architecture?
Based on VNA, but also uses:
1: Pipelining.
2: Cache Memory.
3: Multicore and Parallel Computing.
