1.1.1 Structure and function of the processor

Question 1

What components are within the CPU?

Answer 1

Control unit
Buses
Arithmetic/Logic unit
Dedicated registers

Question 2

What is the function of the control unit?

Answer 2

To control and coordinate the activities of the CPU.

Question 3

What is a bus?

Answer 3

A bus is a set parallel wires connecting two or more components.

Question 4

What does the address bus do?

Answer 4

Sends information of where the data needs to go by sending the address to a memory. and is a signal direction bus from the CPU to the RAM.

Question 5

What does the data bus do?

Answer 5

Sends data to the memory or receives data from the memory and is a bi directional bus.

Question 6

What does the control bus do?

Answer 6

To transmit command, timing and specific status information between system components.

Question 7

What is the definition of a register?

Answer 7

A small piece of memory used for storing data within the processor.

Question 8

What are the five registers?

Answer 8

PC (Program counter), ACC (Accumulator), MAR (Memory address register), MDR (Memory data register), CIR (Current instruction register).

Question 9

What is the function of a program counter?

Answer 9

Holds the address of the next instruction to be executed.

Question 10

What does the CIR do?

Answer 10

Holds the current instruction to be executed.

Question 11

What does the MAR do?

Answer 11

Holds the address of the memory location where data needs to be fetched or written to.

Question 12

What does the MDR do?

Answer 12

Used to temporarily hold the data read or written from memory and is also known as the memory buffer regisiter.

Question 13

What does the ACC do?

Answer 13

Holds the results of ALU operations.

Question 14

Explain the fetch phase.

Answer 14

The address of the next instruction is copied from the PC to the MAR, the MAR is then copied to the MDR and at the same time the PC is incremented. the contents of the MDR is copied to the CIR.

Question 15

Explain the decode phase.

Answer 15

The instruction in the CIR is decoded and split into opcode and operand.

Question 16

Explain the execute phase.

Answer 16

The appropriate instruction (opcode) is carried out on the operand.

Question 17

What are the three factors effecting CPU performance?

Answer 17

Clock speed
The number of cores
The amount and type of cache memory.

Question 18

How does the clock speed effect CPU performance?

Answer 18

Clock speed refers to clock cycles per second which is measured in Gigahertz which is a billion cycles per second. all processor activities begin on a clock pulse so the faster the speed the faster activities can be executed.

Question 19

How does the number of cores effect CPU performance?

Answer 19

Each core theoretically is able to process a different instruction at the same time with its own fetch-decode-execute cycle. so two cores in theory can make the processor twice as fast.

Question 20

How does amount and type of cache memory effect CPU performance?

Answer 20

When a instruction is fetched from main memory it is copied into the cache so if its needed soon after the fetch time is dramatically improved, therefore the faster the cache is and the bigger it is the more instructions it can store in order to speed up fetch times.

Question 21

How many levels of cache are there?

Answer 21

Three

Question 22

What is level 1 cache

Answer 22

Extremely fast with a small capacity between 2-64kb

Question 23

What is level 2 cache

Answer 23

Fairly fast with a medium capacity of 256kb - 2MB

Question 24

What is level 3 cache

Answer 24

Slower and bigger than the ones below.

Question 25

Describe pipelining.

Answer 25

Whilst an instruction is being executed the next can be decoded and the subsequent one fetched.

Question 26

What is are two features unique to Von Neumann architecture?

Answer 26

Data and instructions stored in the same format.

The same bus for instructions and data to connect the CPU to the Memory and Peripherals.

Question 27

What are two features unique to Harvard architecture?:

Answer 27

Data and instructions stored in different formats.

Separate buses for instructions and data to connect the CPU to the Memory and Peripherals.