1.1.1 Structure and function of the processor Flashcards
(a) The Arithmetic and Logic Unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR). Buses: data, address and control: how this relates to assembly language programs. (b) The Fetch-Decode-Execute Cycle; including its effects on registers. (c) The factors affecting the performance of the CPU: clock speed, number of cores, cache. (d) The use of pipelining in a processor to improve e
What components are within the CPU?
Control unit
Buses
Arithmetic/Logic unit
Dedicated registers
What is the function of the control unit?
To control and coordinate the activities of the CPU.
What is a bus?
A bus is a set parallel wires connecting two or more components.
What does the address bus do?
Sends information of where the data needs to go by sending the address to a memory. and is a signal direction bus from the CPU to the RAM.
What does the data bus do?
Sends data to the memory or receives data from the memory and is a bi directional bus.
What does the control bus do?
To transmit command, timing and specific status information between system components.
What is the definition of a register?
A small piece of memory used for storing data within the processor.
What are the five registers?
PC (Program counter), ACC (Accumulator), MAR (Memory address register), MDR (Memory data register), CIR (Current instruction register).
What is the function of a program counter?
Holds the address of the next instruction to be executed.
What does the CIR do?
Holds the current instruction to be executed.
What does the MAR do?
Holds the address of the memory location where data needs to be fetched or written to.
What does the MDR do?
Used to temporarily hold the data read or written from memory and is also known as the memory buffer regisiter.
What does the ACC do?
Holds the results of ALU operations.
Explain the fetch phase.
The address of the next instruction is copied from the PC to the MAR, the MAR is then copied to the MDR and at the same time the PC is incremented. the contents of the MDR is copied to the CIR.
Explain the decode phase.
The instruction in the CIR is decoded and split into opcode and operand.
Explain the execute phase.
The appropriate instruction (opcode) is carried out on the operand.
What are the three factors effecting CPU performance?
Clock speed
The number of cores
The amount and type of cache memory.
How does the clock speed effect CPU performance?
Clock speed refers to clock cycles per second which is measured in Gigahertz which is a billion cycles per second. all processor activities begin on a clock pulse so the faster the speed the faster activities can be executed.
How does the number of cores effect CPU performance?
Each core theoretically is able to process a different instruction at the same time with its own fetch-decode-execute cycle. so two cores in theory can make the processor twice as fast.
How does amount and type of cache memory effect CPU performance?
When a instruction is fetched from main memory it is copied into the cache so if its needed soon after the fetch time is dramatically improved, therefore the faster the cache is and the bigger it is the more instructions it can store in order to speed up fetch times.
How many levels of cache are there?
Three
What is level 1 cache
Extremely fast with a small capacity between 2-64kb
What is level 2 cache
Fairly fast with a medium capacity of 256kb - 2MB
What is level 3 cache
Slower and bigger than the ones below.
Describe pipelining.
Whilst an instruction is being executed the next can be decoded and the subsequent one fetched.
What is are two features unique to Von Neumann architecture?
Data and instructions stored in the same format.
The same bus for instructions and data to connect the CPU to the Memory and Peripherals.
What are two features unique to Harvard architecture?:
Data and instructions stored in different formats.
Separate buses for instructions and data to connect the CPU to the Memory and Peripherals.
