1.1.1 Structure and Function of the processor

Question 1

What is “Cache”?

Answer 1

A temporary store where instructions or data that are likely to be needed are anticipated and are stored, ready for fast access.

Question 2

Why is “Cache” used?

Answer 2

Because RAM is significantly slower than the CPU, Cache is built into the CPU, reducing any limitation in cycles due to the RAMs speed.

Question 3

What is the definition of a “Core”?

Answer 3

A Core acts as a distinct Processing Unit on the CPU.

Question 4

Why are “Multiple Cores” used?

Answer 4

Having Multiple Cores means separate problems can be worked on at the same time. It also means that a single problem can be worked on by multiple Processing Units, speeding up the overall time it takes to solve the problem.

Question 5

What is “Clock Speed”?

Answer 5

The amount instructions carried out/cycles per second.

Question 6

What is “Clock Speed” measured in? What order do Modern Systems normally run at?

Answer 6

Clock Speed is measured in Hertz.

Modern Computer Systems usually run in the order of Gigahertz (GHz) or 1 Billion cycles per second.

Question 7

What is “Pipelining”?

Answer 7

The process of allowing all (but may not always be the case) parts of the processor to always be doing something instead of sitting idle.

Question 8

What is the benefit of “Pipelining”?

Answer 8

It allows for each step of the Fetch, Decode, Execute Cycle can run at the same time on different instructions. When the first instruction has been Fetched, the next one can be Fetched while the first is being Decoded.

Question 9

When can “Pipelining” occur?

Answer 9

Pipelining can occur if subsequent instructions can be predicted. For example, the Fibonacci Sequence cannot be Pipelined as the previous number is needed to find the next one, meaning the next number of the sequence can only be processed if the previous is known.

Question 10

What is a “Flush”?

Answer 10

This is when the current instructions being Pipelined are cleared from the processor so that another instruction can begin to be Pipelined.

Question 11

What is a “Register”?

Answer 11

Areas of memory within the processor that work at very high speeds so they can be used by the processor without causing a Bottleneck.

Question 12

What is the definition of a “Bottleneck”?

Answer 12

A Bottleneck is where a system stops due to its inability to support the traffic.

Question 13

What is the “PC”, and what does it do?

Answer 13

The “Program Counter” holds the address of the next instruction. Once it copies its contents to the MAR, that value its hold is incremented by one, allowing the CPU to execute in sequence. The contents of the PC can also be changed due to Branching.

Question 14

What is the “MDR”, and what does it do?

Answer 14

The “Memory Data Register” stores the data that is fetched or stored into memory.

Question 15

What is the “MAR”, and what does it do?

Answer 15

The “Memory Address Register” stores the address of the data or instruction to be fetched from or sent to the memory.

Question 16

What is the “CIR”, and what does it do?

Answer 16

The “Current Instruction Register” stores the most recently fetched instruction that needs to be Decoded or Executed.

Question 17

What is the “ACC”, and what does it do?

Answer 17

The “Accumulator” stores the results of calculations made by the ALU.

Question 18

What is the “ALU”, and what does it do?

Answer 18

The “Arithmetic Logic Unit” carries out calculations and logical decisions.

Question 19

What can “General Purpose Registers” be used for?

Answer 19

They can be used temporarily by the CPU to store data instead of sending it to memory.

Question 20

What are “Buses”?

Answer 20

Communication channels through which data can be sent around the computer.

Question 21

What 4 “Buses” do you need to know?

Answer 21

Address, Data, Control and System.

Question 22

What is the role of the “Data Bus”?

Answer 22

It carries data between the processor and the memory.

It is Unidirectional.

Question 23

What is the role of the “Address Bus”?

Answer 23

It carries the address stored in the MAR from the processor to memory.
It is Bidirectional.

Question 24

What is the role of the “Control Bus”?

Answer 24

It sends control signals from and to the CU.

It is Unidirectional.

Question 25

What is the “CU”, and what does it do?

Answer 25

The “Control Unit” sends out signals to synchronise the CPU and the memory. It also controls how data moves around the CPU, as well as how it moves between the CPU and the memory.

Question 26

Explain the “Fetch” part of the Fetch, Decode, Execute Cycle.

Answer 26

The contents of the PC is copied to the MAR.
A signal is sent from the CU to the Memory across the Control Bus to read and fetch memory, with the MAR sending its contents to the Memory along the Address Bus.
The contents of the location stored in the MAR are then sent along the Data Bus to the MDR, with its contents copied to the CIR.
The contents of the PC are incremented by one.

Question 27

Explain the “Decode” part of the Fetch, Decode, Execute Cycle.

Answer 27

The contents of the CIR are sent to the Decode Unit to be Decoded (the Opcode and Operand are ‘translated’ to find what process should be executed on what data).
The contents Decoded by the Decode Unit are copied to the MAR for Execution.

Question 28

Explain the “Execute” part of the Fetch, Decode, Execute Cycle.

Answer 28

A signal is sent along the Control Bus by the CU to read and fetch data from memory, with the contents of the MAR sent along the Address Bus.
The process and data found in Memory is sent along the Data Bus to the MDR, with its contents copied to the ACC.
The ALU then uses the contents stored in the ACC to carry out the calculation or logical decision, with the result being stored in the ACC.

Question 29

Define the features of a “Von Neumann” Architecture.

Answer 29

Single Control Unit.
Works through instructions in a sequence.
Instructions and Data are stored in the same memory unit.
Von Neumann is used in CISC.

Question 30

How does “Harvard” Architecture differ from that of “Von Neumann”?

Answer 30

Harvard Architecture has separate memory units for Instructions and Data.
Harvard is used in RISC.