1.1.1 Structure and Function of the Processor Flashcards
KeyWords-Not Peak Styll
1
Q
Registers
A
- Registers are small memory cells that operate at a very high speed
2
Q
Program Counter
PC
A
- Holds the address of the next instruction to be executed
- Increases in increments of 1
3
Q
Accumulator
ACC
A
- Stores the results from calculations
4
Q
Memory Data Register
MDR
A
- Temporarily stores data that has been read or data that needs to be written.
5
Q
Memory Address Register
MAR
A
- Holds the address of a location that is to be read from or written to.
6
Q
Current Instruction Register
CIR
A
- Holds the current instruction being
executed - Divided up into operand and
opcode.
7
Q
Buses
A
- Set of parallel wires
- Connect 2 or more components inside the CPU
- Width of the bus = number of parallel lines
- Width is dirrectly proportional to the number of bits transferred simultaneously at any given time
- Typically 8, 16, 32 or 64 wires wide
8
Q
Address Bus
A
- Used to transmit the memory addresses specifying where data is to be sent
to or retrieved from - The width of the address bus is proportional to the number of addressable memory locations
- Uni-directional, data sent from MAR to main memory
9
Q
Data Bus
A
- This is used for transporting data and instructions between components.
- Bi-directional between CU and main memory
- Carries 1s and 0s of information being transmitted
10
Q
Control Bus
A
- Used to transmit control signals between internal and external
components. - The control bus coordinates the use of the address and data buses and provides status information between system components.
- Bi-directional between the CU and main memory
11
Q
What are the control signals for a control bus
A
- Bus request: shows that a device is requesting the use of the data bus
- Bus grant: shows that the CPU has granted access to the data bus
- Memory write: data is written into the addressed location using this bus
- Memory read: data is read from a specific location to be placed onto the data bus,
- Interrupt request: shows that a device is requesting access to the CPU
- Clock: used to synchronise operations
12
Q
Arithmetic Logic Unit
ALU
A
- Completes all arithmetical and logical operations
- Arithmetic include: addition, subtraction, division, multiplication
- Boolean include: AND, OR, NOT, TRUE, FALSE, XOR
13
Q
Control Unit
CU
A
- The Control Unit is the component of the processor which directs the operations of the CPU
- Some jobs include:
- Controlling and coordinating the activities of the CPU
- Managing the flow of data between the CPU and other devices
- Accepting the next instruction
- Decoding instructions
- Storing the resulting data back in memory
14
Q
Assembly Language
A
- Uses mnemonics to represent instructions,
for example ADD represents addition - The instruction is divided into operand and opcode
15
Q
Opcode
A
- The opcode specifies the type of instruction to be executed.
16
Q
Operand
A
- The operand contains the data or the address of the data upon which the operation is to be performed
17
Q
Hardware
A
- The physical components of a computer ie:
- Keyboards
- CPUs
- GPUs
18
Q
Software
A
- The programs or set of instructions used to operate a computer and execute specific tasks
- Microsoft word
- Games
- Spotify
19
Q
Periperals
A
- Any external devices that connect to a computer system to provide additional functionality.
- Printers
- Speakers
20
Q
Immediate Access Store (IAS)
A
- Holds the instructions and data ready to be used by the CPU
- AKA RAM, primary memory, main memory
21
Q
Clock Speed
A
- Processor runs to the timings of a clock signal
- Measured in hertz or hz
- Run in Gigahertz
- 4GHz = 4,000,000,000 instructions per second
22
Q
Fetch - Decode - Execute (FDE)
A
- Describes the basic steps a CPU carries out to process an instruction.
23
Q
What happens when we double click a program?
A
- Sending an instruction to the operating system to go and find the program on the hard drive
- Copying the program
- Put the copy in RAM
24
Q
Fetch Stage
A
- The PC is loaded with 0
- The value from the PC (0) is copied to the MAR
- The data from the MAR (0) is sent across the address bus with the instruction to read the data sent across the control bus
- The data from that location in memory (0) is sent down the data bus to the MDR
- The PC is incremented by 1
25
Q
Decode Stage
A
- The data is sent from the MDR to the CIR where it is split into the opcode and operand
- This is sent to the CU to be decoded
26
Q
Execute Stage
A
- The address is copied from the CIR to the MAR
- The instruction within the ‘Instruction
Register’ is carried out (executed) by the
CPU. - If a value is being inputted (INP) the ACC will store the value
27
Q
Reset
A
