1.1.1 - Structure and Function of the Processor Flashcards
1
Q
Components of the CPU
A
- Arithmetic Logic Unit (ALU)
- Control Unit (CU)
- Memory Unit (MU)
- Memory, Control, Data and Address Buses
- Registers
— PC, ACC, MAR, MDR, CIR - Clock
2
Q
Arithmetic Logic Unit (ALU)
A
- Carries out calculations and logic operations
— ie. addition/subtraction/multiplication/division, floating point arithmetic, and greater than/less than - Allows inputs/outputs to and from the processor
3
Q
Control Unit (CU)
A
- Manages the execution of (machine) code
- Sends control signals to the rest of the computer though the control bus
— eg. to to hard drives or graphics cards - Synchronises the execution of instructions using the clock
4
Q
Memory Unit
A
- Stores currently running programmes, files and the operating system
5
Q
Buses
A
- Control Bus: Carries signals around the CPU, and coordinating the FDE cycle
- Address Bus: Carries memory addresses from the processor to memory
- Data Bus: Carries data and instructions between the CPU and RAM
6
Q
Clock
A
- A device that coordinates the activity of the computer during execution
- During one clock cycle, the processor can fetch. decode and execute a simple instruction
- More complex instructions can take place over multiple cycles however
- Processor speed is the number of clock cycles per second, measured in Hz
- Increasing processor speeds, more instructions can be executed, so the computer runs faster
- However, this can cause overheating quickly, damaging the lifespan of the computer
7
Q
Little Man Computer
A
- Limited computer to help understand how computers work
- Only has two registers, the Accumulator and the Programme Counter
- Uses a low-level, one instruction per line style of code
- Uses mnemonics to represent instructions (ie. STA to store a value to the ACC)
- Opcode: Instructions, what to do
- Operand: Data/Address, what to enact the operation on, where the data is stored or where to store the outputted data
8
Q
Von Neumann Architecture
A
- Stores data and instructions in the same location and format
- Makes it easy to program in because you don’t need to specify which memory a piece of data is stored in
- Simpler to manufacture as there are fewer components
- Most programmes are designed for use with this kind of architecture, so compatibility is rarely an issue
- However, you need to be careful where you are writing data to memory as to not overwrite instructions as they are stored in the same location, effectively limiting the size of instructions/amount of data you can have
Von Neumann Bottleneck:
- Fetching instructions from memory is slow
- So it takes longer to retrieve data than to complete the task
- In Von Neumann, both the data and instructions are stored in the same location
- This means that they share the same bus to retrieve data
- So both operations have to wait for the other to complete, wasting time
- This slows the speed of the computer as the processor has to wait in idle whilst data is being written/instructions are being fetched
- Limiting the speed of the computer
- Best use in general purpose machines
9
Q
Harvard Architecture
A
- Instructions and data are stored in separate memory devices
- This means that they can be stored in different formats as well
- Separate busses go to the data and instruction memory respectively
- So data and instructions can be fetched simultaneously, speeding up the execution of a programme
- However, this means that the programmer has to specify which of the memory locations data should be stored in (data or instruction memory), making coding more complicated
- As they are stored separately, they have separate busses
- This allows the computer to fetch and store different data simultaneously, eliminating the Von Neumann bottleneck
- This is more expensive to construct, uses more power to run, and produces more heat as there are more components
- So best used in embedded systems where speed is prioritised, such as in medical equipment or aviation
10
Q
Registers
A
- Small blocks of temporary memory in a computer
- Run at the same speed as the CPU
- Can be general purpose or specific purpose
- General purpose can be used for whatever task that the programmer/compiler needs them for
- Specific purpose can only be used to store a specific type of data, but are integral to the execution of processes in the processor
- Specific purpose registers include: PC, MAR, MDR, CIR, ACC
11
Q
Programme Counter (PC)
A
- Contains the memory address of the next instruction to be fetched
- (Assuming that there are no jump instructions, in which case the address it points to may not be relevant)
- It sends its data to the MAR and is incremented as the first step of the FDE cycle
- It is incremented so that it always holds the location of the next instruction to be executed, rather than the current one
- Stores addresses, not the actual instruction
- If a jump instruction is run, the CPU can change the value of the PC to match the relevant address (ie. for if statements or iteration)
12
Q
Memory Address Register (MAR)
A
- Contains the memory address of the instruction that is currently being fetched
- The address it contains is loaded in from the PC
- The address is taken down the address bus so that it can retrieve the correct next instruction
- Stores the address, not the actual instruction
13
Q
Memory Data Register (MDR)
A
- Contains the next instruction to be executed, the instruction that has just been fetched
- Acts as a buffer between the MAR and the CIR, allowing for pipelining to occur to speed up the execution of a task
- When that instruction is ready to be executed, the data from the MDR is copied into the CIR
- Contains the actual instruction, not its address
14
Q
Current Instruction Register (CIR)
A
- Contains the instruction that is currently being decoded executed
- As copied in from the MDR
15
Q
Accumulator (ACC)
A
- Stores the results of calculations performed by the execution of instructions
16
Q
Cache
A
- Small, temporary store of data located closer to the CPU than RAM/Main Memory
- Contains peices of data that are regularly used
- As the Cache is closer to the CPU, data is retrieved from it much faster than it would be from main memroy
- This means that storing more frequently accessed data in Cache speeds up the execution of a programme, as it removes the idle time whilst instructions are being fetched
- The processor always searches Cache for relevant data first
- If that data us found, it is a Cache Hit
- If not, this is called a Cache Miss
- The data fetched is then loaded into Cache for faster retrieval next time
- If the cache is full, the processor replaces the least recently used data with this new data, as that is the data that is more likely to be accessed again in the near future
- This is called LRU Cache (Least Recently Used Cache)
- If a system has a high proportion of Cache Misses, the overall speed of the sustem will be slowed down considerably
- So increasing Cache size will increase the speed of the system
- However, Cache is more expensive
17
Q
FDE Cycle
A
- The address of the next instruction to be fetched is stored in the Programme Counter
- The address from the PC is copied into the MAR
- The PC is incremented by one, to hold the memory address of the next instruction
- Data in the memory address stored in the MAR is retrieved ffrom memory
- This data is stored in the MDR
- When the previous instruction has finished executing, the instruction from the MRD is copied into the CIR
- The CIR stores the instruction as it is being executeding
18
Q
Pipelining
A
- Improves the efficiency of a programme by fetching the next instruction whilst the current instruction is being executed
- Fetching the next instruction is slow, so can cause idle time and inefficiencies
- To combat this, the computer loads the next instruction whilst the current instruction is being executed
- By having the MAR and MDR work at the same time as the CIR
- This reduces wait times
- However, jump instructions means that the instruction pre-loaded and stored in the MDR might not be the next instruction that the computer actually needs
- The computer can try to predict where the code will jump to to tru and mitigate this, but it doesn’t always come up with the correct answer
- Or if which instruction needs to be fetched is said by the current instruction, the computer can use a NOOP instruction to cause a delay in the pipelining until that result is got, to stop wasted work
- If the instruction is not what is needed, the queue can be ‘flushed’ to remove all of the data from it, so it can start again
19
Q
Factors Affecting CPU Performance
A
Clock Speed: Faster clock speed –> more instructions executed per second –> faster speed
Cores: More cores –> more instructions can be executed at once –> faster speed
Cache: More Cache –> Less wait times –> Faster speed
- However, increasing just one of these doesn’t always guarantee a faster overall speed, as the other factors / way that the programme is written may be causing bottlenecks slowing the computer down elsewhere
