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BH A Level 2024-2026 > 1.1.1 Structure and Function of the Processor > Flashcards

1.1.1 Structure and Function of the Processor Flashcards

1
Q

What does the ALU do?

A

Performs all maths and logic operations

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2
Q

What does the CU do?

A

The control unit:
1. Sends signals to coordinate movement of data through the processor during the FDE cycle
2. Controls the buses
3. Decodes instructions

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3
Q

What are registers?

A

Temporary storage inside the CPU used for a specific purpose. Faster to access than RAM.

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4
Q

What are the registers in the CPU called?

A

ACC, PC, CIR, MAR, MDR

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5
Q

What does the ACC do?

A

The accumulator:
1. Acts as temporary storage for data being processed during calculations
2. Acts as a buffer for input and output operations in the processor
3. Is checked for conditional branching operations

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6
Q

What does the MAR do?

A

Stores the address of the next instruction or data to be accessed in memory

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7
Q

What does the MDR do?

A

Stores data and instructions which have been accessed from memory

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8
Q

What does the CIR do?

A

Holds data to be decoded into opcode and operand

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9
Q

What does the PC do?

A

Stores the address of the next instruction to be processed

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10
Q

What are the three buses?

A

Control bus, data bus, address bus

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11
Q

What does the control bus do?

A

Transmits control signals between the CU and other parts of the system

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12
Q

What does the data bus do?

A

Carries data between different system components

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13
Q

What does the address bus do?

A

Carries a memory address from the CU to memory

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14
Q

Six examples of control signals

A

(data) bus request, (data) bus grant, memory write, memory read, interrupt request, clock

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15
Q

What happens in the Fetch step of the FDE cycle

A
  1. Value in the PC is copied to the MAR
  2. Address in the MAR is sent down the address bus at the same time as a memory read signal is sent down the control bus
  3. The value in stored in the location specified by the address bus is sent to the MDR on the address bus
  4. The value in the MDR is copied to the CIR
  5. The value in the PC is incremented by one
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16
Q

What happens during the decode step of the FDE cycle?

A

The instruction in the CIR is split into opcode and operand.

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17
Q

What happens during the execute step of the FDE cycle?

A

The instruction specified by the opcode is carried out, possibly using the ALU.
Results are stored in the ACC if necessary.
The value of the PC will change if it is a branching instruction.

18
Q

What is a word length?

A

The largest group of digits that can be considered at a single time by the processor.

19
Q

What is an opcode?

A

The first part of a machine code instruction, specifies the instruction to carry out.

20
Q

What is an operand?

A

The second part of a machine code instruction, specifies the data the instruction will be carried out on.

21
Q

What are the three LMC branching instructions?

A

BRA, BRZ, BRP

22
Q

What does the LMC SUB instruction do?

A

Performs subtraction using the ALU
Stores the result in the ACC

23
Q

What does the LMC ADD instruction do?

A

Performs addition using the ALU
Stores the result in the ACC

24
Q

What does the LMC STA instruction do

A

Stores the value in the ACC at a specified memory address

25
Q

What does the LMC LDA instruction do?

A

Loads a specified value into the ACC

26
Q

What does the LMC INP instruction do?

A

Waits for input

27
Q

What does the LMC Output instruction do?

A

Outputs a value

28
Q

What does the LMC HLT instruction do?

A

Ends the program

29
Q

What does the LMC DAT instruction do?

A

Reserves a memory location for data

30
Q

What does the LMC BRA instruction do

A

Branches to the specified location, always

31
Q

What does the LMC BRZ instruction do?

A

Branches to the specified location if the value in the ACC is zero.

32
Q

What does the LMC BRP instruction do?

A

Branches to the specified location if the value in the ACC is zero or positive.

33
Q

What are the three factors effecting the speed of the CPU?

A

Cache size and level, number of cores, clock speed

34
Q

How does cache effect the speed of the CPU?

A

Time taken to access instructions in RAM is often a limiting factor in the FDE cycle
Cache is faster to access than RAM because it is closer to the CU
A larger cache means more instructions can be stored and RAM needs to be accessed less frequently
Lower levels of cache are faster to access than higher levels of cache

35
Q

How does the number of cores effect the speed of the CPU?

A

The higher the number of cores the more independent FDE cycles can be completed per second, if the software allows for multi-core processing

36
Q

How does clock speed effect the speed of the CPU?

A

Higher clock speed means more cycles per second, which means more instructions can be executed per second, so the program takes less time to run.
Clock speed can be increased with overclocking.

37
Q

Explain pipelining

CPU piplining

A

An instruction can be fetched as the previous one is being decoded and the one before that is being executed, causing the program to run faster because all parts of the CPU can be used at once.
In the case of a branch the pipeline is flushed.

38
Q

What are two computer architectures called?

A

Harvard, Von-Neumann

39
Q

What are the differences between Harvard and Von-Neumann architecture?

A
  1. Harvard has separate memory for instructions and data, VN has shared memory.
  2. Harvard has separate buses for instructions and data, VN has shared buses.
  3. In Harvard the size of instruction and data memory is fixed. In VN the amount of the shared memory allocated to instructions or data can change.
  4. In Harvard the instruction memory may be read only. In VN the instructions and data are stored in the same format.
40
Q

How is modern computer architecture different from traditional Von-Neumann architecture?

A

Pipelining, cache, multiple cores, overclocking, seperate instruction and data cache

41
Q

Which LMC instructions will change the value in the ACC?

A

ADD, SUB, LDA, INP

42
Q

Which LMC instructions will change the value in the PC?

A

BRA, BRZ, BRP

BH A Level 2024-2026 (4 decks)

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