1.1.1 STRUCTURE AND FUNCTION OF THE PROCESSOR

Question 1

Program Counter (PC)

Answer 1

Holds the address of the next instruction to be executed

Question 2

Accumulator (ACC)

Answer 2

Stores the results from calculations

Question 3

Memory Address Register (MAR)

Answer 3

Holds the address of a location that is to be read from or written to

Question 4

Memory Data Register (MDR)

Answer 4

Temporarily stores data that has been read or data that needs to be written

Question 5

Arithmetic Logic Unit (ALU)

Answer 5

Completes the arithmetical and logical operations

Question 6

Control Unit (CU)

Answer 6

Directs operations inside the CPU.
It:
.Controls and coordinates the activities of the CPU
.Manage the flow of data between the CPU and other devices
.Accepting the next instruction
.Decoding instructions
.Stores the result back in memory

Question 7

What are registers

Answer 7

Small memory cells that operate at very high speeds. Used to temporarily store data. All arithmetic, logical or shift operations occur in these registers.

Question 8

Buses

Answer 8

A set of parallel wires which connect two or more components inside the CPU together. The collection of the data bus, control bus, and address bus is called the system bus. The width of the bus is the bumper of parallel wires the bus has.

Question 9

Data bus

Answer 9

A bi-directional bus used for transporting data and instructions between components.

Question 10

Address bus

Answer 10

Used to transmit the memory addresses specifying where data is to be sent to or retrieved from. Adding a wire to the address bus doubles the number of addressable locations

Question 11

Control bus

Answer 11

This is a bi-directional bus used to transmit control signals between internal and external components.

Question 12

Clock speed

Answer 12

Determined by the system clock. All processor activities begin on a clock pulse. Each CPU operation starts as the clock changed from 0 to 1. The clock speed is the number of clock cycles completes in a second.

Question 13

Number of Cores

Answer 13

A core is an independent processor that is able to execute its own fetch-execute cycle. A computer with multiple cores can complete more than one fetch-execute cycle at any given time. Some programs aren’t optimized for the use of more than one core.

Question 14

Cache memory

Answer 14

The CPU’s onboard memory. Instructions fetched from main memory are copied to the cache, so if required again it can be accessed quicker. As cache fills up, unused instructions get replaced.

Question 15

Pipelining

Answer 15

The process of completing the FDE cycles of three separate instructions simultaneously. Data is held in a buffer in close proximity to the CPU until it’s required. Pipelining is aimed to reduce the amount of the CPU which is kept idle.

Question 16

Von Neumann Architecture

Answer 16

Includes a single CU, ALU, registers and memory units. Shared memory and data bus used for both data and instructions.
BENEFITS: cheaper to develop since the CU is easier to design. Programs can be optimized in size

Question 17

Harvard Architecture

Answer 17

Physically separate memories for instructions and data. More commonly used with embedded processors.
BENEFITS: Quicker since data and instructions can be fetched in parallel. Both memories can be different sizes.

Question 18

Contemporary processing

Answer 18

Combination of Harvard and Von Neumann. Uses VN when working with the data and instructions in main memory. Uses H when working with cache. There is an instruction cache and a data cache.

Question 19

FDE cycle

Answer 19

The FDE cycle is a sequence of operations that are complete in order to execute an instruction.

FETCH: Address from the PC is copied to the MAR. Instruction held at that address is copied to MDR by the data bus, simultaneously the contents of the PC are increased by 1. The value held in the MDR is copied to the CIR.

DECODE: The contents of the CIR are split into operand and opcode.

EXECUTE: The opcode is executed on the operand