1.1.1 Structure and function of the processor

Question 1

Control Unit

Answer 1

part of the processor that coordinates the activity of all other components

Question 2

Control Signals

Answer 2

signals sent along the control bus between the control unit and other components

Question 3

Control Signal: Memory Read

Answer 3

data from the addressed location in RAM to be placed on the data bus

Question 4

Control Signal: Memory Write

Answer 4

data on the data bus to be written into the addressed location in RAM

Question 5

Control Signal: Bus Request

Answer 5

indicates that a device is requesting
use of the data bus

Question 6

Control Signal: Bus grant

Answer 6

indicates that the CPU has granted access to the data bus

Question 7

Control Signal: Clock

Answer 7

Used to synchronise operations

Question 8

Bus

Answer 8

Series of connectors that transfer signals

Question 9

System Bus

Answer 9

Three separate buses carrying control signals, addresses and data

Question 10

Arithmetic Logic Unit (ALU)

Answer 10

Performs logical, arithmetic and shift operations

Question 11

Accumulator (ACC)

Answer 11

register of super-fast memory that stores results from ALU

Question 12

Program Counter (PC)

Answer 12

holds the memory address of next instruction

Question 13

Current Instruction Register (CIR)

Answer 13

holds the current instruction and split into opcode and operand

Question 14

CIR: Opcode

Answer 14

specifies the operation to be carried out

Question 15

CIR: Operand

Answer 15

contains address of data to be copied to MAR
OR
contains actual data to be operated on to be passed to MDR

Question 16

Memory Address Register (MAR)

Answer 16

holds the address of memory location

Question 17

Memory Data Register (MDR)

Answer 17

holds the data moving between the processor and memory

Question 18

Fetch Stage: Component order

Answer 18

PC -> MAR
MAR -> MDR (PC + 1)
MDR -> CIR

Question 19

Fetch Stage (PC -> MAR)

Answer 19

Address of next instruction is copied from PC to MAR

Question 20

Fetch Stage (MAR -> MDR {PC + 1})

Answer 20

Instruction at address in MAR is copied to MDR, simultaneously the PC is incremented by 1

Question 21

Fetch Stage (MDR -> CIR)

Answer 21

Content in MDR is copied to CIR

Question 22

Decode Stage (CIR)

Answer 22

The instruction in the CIR is decoded

Question 23

Decode Stage (CIR)

Answer 23

Splits into Opcode and Operand to determine type of instruction

Question 24

Opcode

Answer 24

What operation needs to be carried out

Question 25

Operand

Answer 25

Holds the address for the operation OR the actual data for the operation

Question 26

Decode Stage (CIR to Accumulator)

Answer 26

The instruction is then passed on to the accumulator

Question 27

Execute Stage

Answer 27

The result is held in the accumulator and the control unit sends a signal along the control bus to main memory