1.1.1 Structure and function of the processor Flashcards

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1
Q

Function of an ALU

A

Performs all the mathematical and logical calculations.

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2
Q

Function of an Accumulator

A

Stores the intermediate results performed by the ALU.

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3
Q

Function of a program counter

A

Holds the address of the current instruction to be executed.

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4
Q

Function of an MAR

A

Holds the address of a location that is to be read or written from.

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5
Q

Function of an MDR

A

Stores the data that has been read or need to be written to.

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6
Q

Function of an CIR

A

Holds the current instruction being executed and splits it into operand and opcode.

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7
Q

What is a Control Bus?

A

Bi-directional bus that transmits Control signals between components.

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8
Q

What is a Data Bus?

A

Bi-directional bus that transports data and instructions between components.

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9
Q

What is a Address Bus?

A

Transmit memory addresses specifying where the data should be sent or retrieved from.

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10
Q

Describe the FDE Cycle

A

1) Address from PC gets copied into the MAR
2) Instruction from this address gets copied into MDR
3) PC is incremented by 1
4) Data from MDR copied into CIR
5) Data in CIR is split into opcode and operand
6) Instruction gets executed

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11
Q

What are the 3 factors that affects CPU performance?

A
  • Clock Speed
  • Number of Cores
  • Amount of Cache
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12
Q

How can Clock Speed affect CPU performance?

A

Clock Speed is the number of FDE Cycles that can be done per second. The higher the Clock Speed the more instructions executed each second.

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13
Q

How can Number of Cores affect CPU performance?

A

More cores means each core can do different tasks simultaneously. Therefore improves CPU performance as you can execute lots of instructions at once.

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14
Q

How can Amount of Cache affect CPU performance?

A
  • Cache is a fast memory that stores frequently used data. Meaning when the data is needed, CPU won’t have to fetch it from main memory which is much more faster.
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15
Q

What is Pipelining?

A

Where Instruction is being fetched, Decoded and executed at the same time simultaneously. Branching occurs where useless information is fetched by the CPU, we will need to flush the pipeline then.

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16
Q

The Difference between Von Neumann architecture, Harvard architecture and Contemporary processing?

A

Von Neumann: Stores data and instructions in the same memory
Harvard architecture: Stores data and instructions in 2 dedicated memories
Contemporary processing: Uses Von Neumann when working with data and instructions in main memory and uses Harvard architecture to split cache into data and instruction cache.