1.1.1 Structure and function of the processor Flashcards

1
Q

Arithmetic Logic Unit ALU

A

Performs:
- Arithmetic Operations (subtract/multiply/divide) on fixed/floating point numbers.
- Logical Operations (AND/OR/NOT)
-Shift bits left or right within a register

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2
Q

Control Unit (CU)

A

Controls & coordinates activities of the CPU => directs flow of data.
Accepts the next instruction, decodes it into sequential steps, manages its execution, and stores data back into memory/registers.

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3
Q

Program Counter (PC)

A

Holds the address of the next instruction to be executed.

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4
Q

Current Instruction Register (CIR)

A

Holds the current instruction being executed (divided into operand/opcode).

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5
Q

Memory Address Register (MAR)

A

Holds the ADDRESS of the memory location from whom data is to be fetched/written.

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6
Q

Memory Data Register (MDR)

A

Used to temporarily store the data read from/written to memory.

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7
Q

Control Bus

A
  • Bi-directional, so signals can be carried in both directions.
  • Transmit command, timing, and specific status information between system components.

Examples of control lines: Bus Request, Bus Grant, Memory read/Write, Interrupt request, Clock

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8
Q

Data Bus

A
  • Consists of 8, 16, 32, or 64 separate lines.
  • Provides a bi-directional path from moving data and instructions between system components
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9
Q

Address Bus

A
  • Each word (fixed-size groups of digits) in memory has its own address.
  • The address bus transmits the memory addresses of words that are used as operands in program instructions so that data can be retrieved/sent back to the processor.
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10
Q

Fetch Phase

A
  • Address of the next instruction copied from the PC to the MAR.
  • Instruction held at that address is copied to MDR. Simultaneously, the PC is incremented.
  • Contents of the MDR copied to the CIR.
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11
Q

Decode Phase

A

The instruction held in the CIR is decoded & split into either:
- Operand, which holds the address (copied to MAR), data (copied to MDR)
- Opcode, which is the type of instruction/hardware.

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12
Q

Execute Phase

A

The appropriate opcode is carried out on the operand.

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13
Q

Clock Speed on processor performance

A
  • The system Clock generates a series of signals to synchronise CPU operations.
  • The greater the clock speed => the faster instructions will be executed.
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14
Q

Number of Cores on processor performance

A
  • Each core can process a different instruction at the same time with its own fetch-execute cycle.
  • It does not always perform twice as fast, because the software may not always be able to take full advantage of both processors.
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15
Q

Amount/Type of Cache Memory on processor performance

A
  • Cache is a small amount of expensive, fast memory in the CPU.
  • When an instruction is fetched from main memory, it is copied into cache so that when it is needed again, it can be fetched from cache, which is quicker.
  • Different levels of cache: Level 1 (very fast/small), Level 2 (fairly fast. medium)
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16
Q

Pipelining

A

The next instructions are fetched at the same time as the processor is performing arithmetic/logic operations.

17
Q

Von Neumann Architecture

A
  • Data & Instructions share the same memory
  • One bus is used to transfer data and instructions
  • Programs can be optimised in size
    -Used in conventional processors in PCs/servers/embedded systems with only control functions
18
Q

Harvard Architecture

A
  • Data & Instructions are held in separate memories
  • Parallel data and instruction buses can be used
  • Programs tend to be large
  • Used in digital signal processing/embedded systems/mobile communication systems etc.
19
Q

Contemporary Processor Architectures

A
  • Combine aspects of both Von Neumann/Harvard
  • One main memory for holding data/instructions
  • CPU cache memory divided into instruction/data cache. Harvard architecture is used as the CPU accesses this cache.
  • Multiple parallel data buses and one instruction bus