1.1.1 - Structure and Function of the Processor

Question 1

What is the CIR and what is its purpose?

Answer 1

Current Instruction Register (CIR) - Holds the instruction while it is being decoded/executed.

Contents are split into opcode and operand

operand is copied to MAR if it is an address or MDR if it is data

Question 2

What is the MDR and what is its purpose?

Answer 2

Memory Data Register (MDR) - Contains the instruction or data which has been accessed from memory

Question 3

What is the MAR and what is its purpose?

Answer 3

Memory Address Register (MAR) - Contents of the PC are copied here in order for the processor to access the next instruction

Question 4

What is the ACC and what is its purpose?

Answer 4

Accumulator (ACC) - Temporary storage for data being processed (input and output) - Holds results of calculations (from the ALU)

Question 5

What is the PC and what is its purpose?

Answer 5

Program Counter (PC) - Stores the address of the next instruction to be fetched

Question 6

What is the CU and what is its purpose?

Answer 6

Control Unit (CU) – Decodes instructions and sends out control signals

Question 7

What is the purpose of the address bus?

Answer 7

Address Bus – Carries the address where the data is going to or from

Question 7

What is the ALU and what is its purpose?

Answer 7

The Arithmetic and Logic Unit (ALU) - Carries out calculations and logical instructions

Question 8

What is the purpose of the data bus?

Answer 8

Data Bus - Carries the data from one place to another

Question 8

What is a register?

Answer 8

Register - Small piece of temporary memory located within the processor/CPU. Used for a specific purpose.

Question 9

What is the purpose of the control bus? What CPU component would use this bus?

Answer 9

Control Bus - Carries control signals from the control unit to other parts of the system

Question 10

What are the sub-stages of the fetch part of the FDE cycle?

Answer 10

1. Data/address is copied from PC to MAR
2. PC is incremented (usually by 1)
3. Data in MAR is passed onto the Address Bus
4. Conrol unit sends read signal onto the control bus
5. RAM copies the data from the location specified by the address bus along the data bus
6. Data on the data bus is stored in the MDR
7. Data is copied from the MDR to the CIR

Question 11

What are some key facts about the Von Neumann Processor

Answer 11

• Data and Instructions are stored in the same area of memory in the same format
• Uses the same bus for data and instructions - can only fetch either data or instructions at one time
• Design is less complex - development is cheaper
• Single CU / ALU
• Uses the special registers (MDR, ACC etc..)
• Follows the Fetch Decode Execute cycle

Question 12

What are some key facts about the Harvard Processor

Answer 12

• Separate memory for instructions and data - could fill unequally
• Has separate data and address buses for instructions
• Can read/write data and instructions simultaneously
• Has fixed memory sizes for data and Instructions
• Development is more expensive. More CPU pins are required; a complex motherboard is required with doubling of memory

Question 13

What is a contemporary architecture and what features may it have?

Answer 13

AKA - Modern Processors - Has aspects of both Von Neumann and Harvard.

Have features such as:

• Pipelining
• Make use of cache
• Virtual Cores
• Hyper Threading
• Multiple Cores
• On-board Graphics

Question 14

What are the recognised factors affecting the performance of a CPU?

Answer 14

1. Clock Speed
2. Number of Cores
3. Cache Size/Speed

Question 15

How does the clock speed influence the performance of the CPU?

Answer 15

The speed at which the fetch decode execute cycle is completed. Higher clock speed gives more cycles per second meaning more instructions can be executed per second (program takes less time to run)

Question 16

How does the number of cores influence the performance of the CPU?

Answer 16

Each core is a processing unit, giving the potential for multiple instructions to be run at the same time

Question 17

How does the cache size influence the performance of the CPU?

Answer 17

High levels of cache give more space for data/instructions so slower RAM needs to be accessed less frequently.

Question 18

What is pipelining? What are the benefits?

Answer 18

Concurrent processing of multiple instructions – increases the number of instructions processed in a set period of time.

Would allow one instruction to be fetched as the previous one is being decoded and the one before that is being executed.

Prevents the CPU having to wait – No idle components

Question 19

What issues does pipelining face?

Answer 19

Struggles with code that uses branching, as wrong instruction may be brought, meaning flush would be used.