111-structure-and-function-of-the-processor

Question 1

Computer

Answer 1

• process data by following instructions in a program using CPU and main memory.
• store and retrieve data from storage devices (e,g hard drives, solid-state drives, and USB drives)
• electronic device: performs a wide range of tasks…
  -…from basic calculations to complex data processing and multimedia tasks.

Question 2

Processor/CPU

Answer 2

• FDE continuously
  drives overall operations of system and controls other components of the system
• Processes data by executing program instructions
• regularly interacts with main memory.

Question 3

CU

Answer 3

• Coordinates + synchronizes CPU activities and all other processor components.
• Manages FDE cycle phases.
  decodes and determines appropriate ensuring-correct sequence of operations to carry out for execution of instruction
• Sends/receives control signals that direct flow of data and instructions between the computer’s components (ALU, I/O devices, memory, etc.) and checks if signals been delivered successfully.
• stores the resulting data back in memory
• Typically made up of a clock and a decoder.

Question 4

ALU

Answer 4

performs logical and arithmetic operations (calculations on fixed n floating point numbers (e.g addition), logical comparisons (eg greater than), logical bitwise operations (e.g XOR), binary shifts).

Question 5

IAS (immediate access store)

Answer 5

holds instructions n data ready to be used by CPU. Set of memory locations. Also called main memory/RAM/primary memory

Question 6

System clock

Answer 6

• electronic unit
• synchronises flow of data (to avoid accidental overwriting data) n all processor components operations by generating signal pulses at a regular constant rate
• that continuously switches between a low (0)and a high (1) state. Rising edge- low to high, falling edge- high to low state. All processor activities begin on a clock pulse

Question 7

Clock cycle

Answer 7

• clock period= time taken between two sequential rising edges, corresponds to 1 clock cycle
• Every operation of processor typically requires a number of clock cycles to complete, specific to each type of processor.
• E.g fetching data from memory/data transfers could require many clock cycles

Question 8

Clock speed/rate/frequency

Answer 8

• number of FDE cycles ran per sec, measured in hz
• determined by system clock
• Higher clock speed= more processing it can do per sec+ more instructions executed faster rate so programs execute faster
• Clock rate=1/clock cycle time

Question 9

Overclocking

Answer 9

• Overclocking = increasing component’s clock speed beyond its intended limit by adjusting BIOS or firmware settings.
• can improve performance but also generate heat, reduce lifespan, and cause instability or crashes if not properly managed.
• To compensate for the increased heat, overclockers typically use more powerful cooling solutions.

Question 10

Decode unit

Answer 10

• piece of logic presented with a sequence of bits fetched from memory.
• prepares execution of an instruction by looking up the binary operation code in its table so CPU knows what to do.
• Fixed commands available in unit specific to instruction set architecture of processor

Question 11

Registers

Answer 11

• small fast memory locations within processor with a single specific purpose.
  @
• Provides extremely faster access than RAM/secondary storage, temporarily stores data/instructions/address.
• General-purpose registers & special-purpose registers

Question 12

General-purpose registers

Answer 12

• to temporarily store n access results of operations for quicker retrieval n execution
• e.g ALU is connected to a set of general purpose registers: stores temporary intermediate calculation values produced as part of a larger computation whilst ALU is carrying out a calculation

Question 13

Dedicated/special-purpose registers

Answer 13

processor-based registers used for a specific purpose. E.g the registers used in the FDE

Question 14

Program counter (PC)

Answer 14

holds address of next instruction to be executed and copies it to the MAR. Increments by to point in the next instruction with each cycle.

Question 15

Accumulator (ACC)

Answer 15

stores arithmetic and logic results of ALU
- stores inputs and outputs
- stores intermediate/working value
- stores data loaded from MDR/RAM
- checked for conditional branching e.g BRZ

Question 16

Memory Address Register (MAR)

Answer 16

stores memory location address of data/instructions to be fetched/executed, or where data will be written to. Connected to address bus which carries address to RAM

Question 17

Memory Data Register(MDR)/memory buffer register

Answer 17

holds data (data values/instructions) read from/to write to RAM, next to be processed, Connected to data bus. Contents of MDR copied to CIR too if it’s a instruction

Question 18

Current instruction register (CIR)

Answer 18

holds current instruction being executed, divided up into operand and opcode, copied from MDR

Question 19

Buses

Answer 19

• high-speed internal communication system
• consists of a set of parallel connections
• used to transport instructions & data, control signals, addresses,
• between the processor and components of computer system.

Question 20

How can buses be implemented

Answer 20

various physical media, such as wires, optical fibers, or even wireless communication protocols. The specific implementation depends on the requirements of the computer system, such as the speed and distance of communication needed between components.

Question 21

System bus

Answer 21

connect CPU, main memory and I/O controllers( internal components) n allow communication w/ eachother. Made up of address, data and control bus.

Question 22

External bus

Answer 22

used to connect the peripherals to the processor. Can be serial/parallel connections.

Question 23

Address bus

Answer 23

carries addresses that identifies where to write data/instructions to/read from. unidirectional from processor to main memory

Question 24

Address bus width

Answer 24

determines number of bits that can be used to form an address of a memory location. Greater width= more addressable memory locations. E.g width 8 bits= 2^8 memory locations

Question 25

Address space

Answer 25

Max addressable memory locations
- determined by width of address bus, memory capacity of computer system.
- Affects processor performance (larger main memory to access data and instructions reduces reliance on VM)

Question 26

Data bus

Answer 26

carries binary data/instructions between stated memory locations. Bi-directional. Data transferred to/from processor, to/from main memory, to/from I/O controllers.

Question 27

Data bus width

Answer 27

number of parallel lines, determines number of bits that can be transferred in one operation simultaneously. Greater width, more/larger data can be passed at a time, better processor performance as reduces time taken for data/instructions to be processed/less retrievals/fetches. if width 8 bits, =1 byte of data.

Question 28

Control bus

Answer 28

transmit control signals and commands between internal components of CPU & external components. Coordinates use of address & data buses, & operations of components, provides status info between system components. Bi-directional.

Question 29

Control signals types

Answer 29

memory read- places data from specific memory location (address on address bus) onto data bus. memory write - stores data from data bus onto specific memory location (address on address bus). bus request - signifies a component needs to access a bus. bus grant- signifies component is informed it can use the bus it requested access to. bus busy- signifies bus not available for use (e.g is used by another component), interrupt request - signifies error/exception has ocr rued that requires attention of CPU, clock signals - clock pulses generated by system clock

Question 30

Control signal uses

Answer 30

request communication between 2 units, acknowledge a communication request, specific type of data being transferred via other buses (e.g data values/instructions/addresses), synchronise operations/communication between components using clock pulses

Question 31

FDE cycle simplified

Answer 31

to process data. Instruction fetched from RAM, instruction decoded, instruction executed. Process repeated. CPU performs continuously, repetitive cycle.

Question 32

FDE cycle (fetch stage)

Answer 32

PC holds address of next instruction to be executed, contents of PC copied to MAR. Address sent along address bus to main memory, awaits a signal from control bus. CU sends memory read signal along control bus to main memory so data in the addressable memory location can be fetched. Ram copies the contents specified in the address bus onto the data bus, sent along to MDR(from main memory to processor) and stored in MDR, then gets copied into CIR (if instruction). Simultaneously, the contents of PC increments it points to address of next instruction that needs to be fetched. If the current instruction is to branch, PC adapts to point to the right address. Otherwise PC increments by 1.

Question 33

FDE cycle (decode stage)

Answer 33

instruction held in CIR gets decoded by CU. Splits instruction into operand (an address/actual data) and opcode (instruction). Opcode decoded using instruction decoder (uses instruction set for CPU to work out what to do with operand)

Question 34

FDE cycle (execute stage)

Answer 34

instruction is executed. Sequence of operations depends on instruction type being executed. Result is stored in the accumulator/general purpose register/main memory.

Question 35

Cores

Answer 35

• additional processing unit
• run its own FDE cycle n accessing dedicated L1 cache and registers
• Allows multitasking/parallel processing
• simultaneously execute instructions
• run different parts of program at same time
• process instructions independently of eachother
• processes can be split between cores n processed faster w more completed per sec

Question 36

When do cores not improve CPU performance

Answer 36

• software not designed for multiple cores
• some tasks cannot be split between across multiple cores. (t: if cannot split, system have to queue parts of instruction being fed to particular core - slows completion)
• other factors affect performance (e.g lower clock speed n ram size). - cores have to communicate w eachother, more cores=more communication, synchronisation and organisation, which receives which data n instructions= overheads -> costs time n efficiency.

Question 37

Cache

Answer 37

• local volatile fast small memory kept on/close to processor
• stores frequently/recently/next to be used used instructions n data for faster access than to n from RAM
• Increasing= more data transferred faster n more instructions quicker access n fetch + carried out (efficient, save time)
• too much= detrimental, longer for CPU to find specific data/instructions.

Question 38

Cache levels

Answer 38

L1= extremely fast, small capacity (apart of processor chip itself - reduce time takes for instructions/data to pass through system registers). L2=relatively fast, shared by cores, medium capacity, usually apart of processor. L3= slower, shared by cores, larger capacity, sits on or near processor.

Question 39

Pipelining

Answer 39

• series of instructions completed concurrently - Parallel processing of multiple instructions. increases speed of execution.
• so as instruction fetched, previous can be decoded and one before that executed continuously.
  -output to one operation is input to the next
• CPU is not idle while waiting for next instruction, efficient
• technique: continuous, overlapped, orderly movement of instructions or arithmetic steps.
• reduces/avoids amount of processor and internal components kept idle
• all parts of processor can be used at any instance in time. reduces/remove latency,
  – task needs to be able to be broken down into sub tasks that can be handled independently
• Makes efficient use of cpu time but pipelined CPUs more expensive
• If Program w/ lots of branch instructions: if need to jump elsewhere to fetch instruction, need to flush pipe and remove the other instructions, the ones already fetched/decoded. + certain instructions may need to be run first as result needed for next instruction to be ran (can’t use pipelining on conditionals/selection). another approach is to process the next instruction in all possible branches and abandon the ones not needed later determined at execution (inefficient).

Question 40

The two types of pipelining

Answer 40

• instruction pipelining: separating out the instruction into fetching, decoding, executing (used in completing FDE cycle simultaneously. Appropriate data held in buffer in close proximity to CPU until required
• arithmetic pipelining - break down arithmetic operations n overlapping them as they are performed
• pipelining in gen: splitting task into smaller tasks and overlapping them

Question 41

Von Neumann Architecture

Answer 41

• Data n instructions stored in same memory (RAM) together and transferred using a single shared bus.
• shared address and data bus.
• can only fetch either data or instructions at one time
  @
  Single CU, single ALU, registers, memory units (that communicate directly w/processor). Registers used as fast access to instructions n data.
• execute programs by doing one instruction at a time after the next serially (in order), using FDE cycle.
• program must be loaded into main memory to be executed by processor
  -Built on stored program concept.
• Used in PCs, laptops, servers, high performance computers, general purpose computers (expected to accommodate varying end user needs e.g run numerous applications and switch between tasks)

Question 42

Von Neumann Architecture pros

Answer 42

• flexible use of main memory: can use free memory for data/instructions (as same memory)
• Simpler easier CU design = cheaper to build computers
• different programs can be optimised (stored program concept) so processor can run variety of programs not known in advance.
• Same data n address bus = simpler for control.

Question 43

Von Neumann Architecture Cons

Answer 43

• bottleneck: instructions cant be fetched at same time as data
• takes time to send data/instructions along address/data bus as shares same pathway (causes latency)
• instructions+data in same memory= exploitable by hackers (disguise malware instructions as data that processor may execute unknowingly when attempting to read data)

Question 44

Stored program concept

Answer 44

• Idea of where Main memory unit stores both programs and data
• Instructions can be fetched and executed sequentially from main memory
• Enables versatility and ability to perform a variety of tasks
• Allows different programs to be loaded and executed on the same machine architecture
• Enables machines to perform different tasks without needing to be reprogrammed for each task
• Led to the creation of general-purpose computers.

Question 45

Harvard Architecture

Answer 45

• Held in physically separate memories (one for instruction, other for data) with their own dedicated data buses and address buses.
• Data n instructions can have different word lengths n bus widths, and different sized memories.
• Used in where speed is more important than design complexity e.g digital signal processing, microcontrollers, embedded systems e,g microwaves, ovens n watches, by RISC processors, situations where speed of operation is important e.g embedded system traffic control cameras (process large amounts of data in real time)

Question 46

Harvard architecture pros

Answer 46

• Separation of data and instructions in different memory modules prevents errors caused by data overwriting instructions and vice versa.
• Can have different memory sizes and structures, allowing for more efficient use of space.
• Different memory characteristics can be used for instructions and data, providing better protection against hacking.
• Potentially faster processing speed due to simultaneous fetching of instructions and data.
• Allows for parallel processing.

Question 47

Harvard architecture cons

Answer 47

• More complicated and expensive control unit required for managing two separate buses.
• Instructions cannot use the data memory space, and data cannot use the instruction memory space.

Question 48

Contemporary processor architecture

Answer 48

• Combines elements of the Harvard and von Neumann architectures, with separate caches for instructions and data.
• Uses cache to store frequently used data and instructions in a small amount of high-performance memory next to the CPU.
• Utilizes onboard graphics circuitry for graphics processing.
• Uses virtual cores/hyper-threading to treat a physical core as two virtual cores, improving efficiency.
• Employs different sets of buses and memories to allow for concurrent access to instructions and data.
• Utilizes multiple cores and pipelining for efficiency, including SIMD for parallel processing and MIMD for carrying out multiple instructions on multiple data across several cores.
• Supports distributed computing, in which multiple computers on a shared network work together to solve a larger problem.

Question 49

Input/output I/O controllers

Answer 49

• Input-output controllers manage data transfer between the computer and peripherals
• They serve as an interface between the computer system and peripherals for data exchange, including secondary storage
• They are connected to the processor through physical ports, which can include specialist controllers in larger desktop computers
• Each peripheral device has its own I/O controller or share hub controller
• The controller translates electrical signals between the processor and peripheral into the correct form
• Input data can be received from input devices, stored in the I/O controller, and processed by the processor
• Results of computation are outputted from the system to output devices
• I/O controllers provide a set of addressable registers that the CPU accesses to communicate with I/O devices
• They also have a buffer to accommodate timing and sync, since peripherals operate at slower speeds than the processor.

Question 50

Word length/size

Answer 50

• Word length is the amount of data that can be handled at one pass by the processor, always a multiple of 8.
• The size of the bit pattern/number of bits that can be transferred to/from main memory in one operation is determined by word length.
• The size of processor registers is designed to be equal to word length.
• Data bus width is also equal to word length.
• Each addressable memory location in main memory is the size of a word in a word-addressable design.
• A larger word size allows for a greater amount of data and instructions to be accessed and transferred to the CPU in one pass.
• Having a larger word size is likely to carry out instructions faster if processing instruction require multiple fetches of data since there are fewer passes required.

Question 51

Improving Computer’s Performance

Answer 51

• Check memory usage: Use Task Manager to check if all RAM is being used. Adding more RAM can improve performance (!!! if its full)
• Clear cache and temporary files: This can help free up valuable storage space and improve performance.
• Close unnecessary processes: Terminating unused processes can free up memory and improve performance, but be careful not to close anything critical to the system.
• Manage startup programs: Too many programs running at startup can slow down the computer’s performance.
  -Defrag the computer: Defragmenting can improve performance (!!!on magnetic hard drives)
  – Update operating system and drivers: Software updates can fix bugs and improve compatibility with hardware and other software.
• Check for hardware issues: Use diagnostic tools to check for any hardware-related issues.
• Install antivirus: Malware can slow down a computer, so installing antivirus software can help identify and remove threats
• Upgrade to an SSD: This can significantly decrease boot-up time and improve program loading times (!!!for a older machine).
• Upgrading CPU: Changing the CPU can improve the number of cores, clock speed, and cache in the CPU, leading to faster processing. However, this can be an expensive option and may require a new motherboard as well to fit the CPU in it (cannot improve cores or etc individually, comes with CPU)
• Upgrading GPU - can improve performance in graphics rendering, but can also be expensive, and only if it’s needed for the context