1.1.1 - Structure and function of the processor

Question 1

What is the ALU?

Answer 1

The ALU is responsible for performing arithmetic calculations and logical operations like:
+-*/
logical bitwise operations like AND OR NOT and XOR
comparisons between values
binary shifts

Question 2

What does the control unit do?

Answer 2

The control unit organises the sequence in which programmes are executed, followed by decoding the instructions.
This means the control unit is responsible for directing the operations of all the other components of the processor.

Question 3

What tasks does the control unit do?

Answer 3

• It uses control signals to enable data to be read from and written to main memory.
• It uses control signals to determine what operation the ALU will carry out.
• It decodes every instruction the processor will execute to determine what needs to be done.
• It organise the sequence of micro-operations that need to be performed in order to carry out an instruction.

Question 4

What does the system clock do?

Answer 4

The clock generates pulses by emitting a signal that oscillates between a low (0) and high (state).
It synchronises the operations of the processor components.
Every operation of the CPU requires a number of clock cycles to complete, specific to each processor.

Question 5

What is a register and what does it provide?

Answer 5

A register is a location of computer memory within the processor that provides extremely fast access, therefore preventing bottlenecks.

Question 6

What is the use of a general purpose register?

Answer 6

Having to access the main memory can slow down the execution of instructions. Therefore, the processor uses registers to temporarily store and access the results of operations.

Question 7

What does the program counter do?

Answer 7

It holds the address of the next instruction to be executed by the processor.

Question 8

When does the program counter change?

Answer 8

It is incremented by one during the fetch phase of the FDE cycle. Instructions which change the flow of control, like branches, also change the PC value.

Question 9

What does the CIR do?

Answer 9

The CIR stores the most recently fetched instruction that is waiting to be decoded and executed.

Question 10

What is the status register used for?

Answer 10

Used to store information about the result of the last instruction that the ALU executed.
Each bit within the status register acts as a flag to indicate if an error or exception has occurred within the process, or to enable or disable interrupts to be raised.

Question 11

What is an error or exception?

Answer 11

An error or exception is when the result of a calculation requires further action. For example, it signifies if the result of a calculation is negative or zero, or if a calculation produced an overflow or/and a carry.

Question 12

What is an interrupt?

Answer 12

An interrupt is an event outside of the program process which requires the attention of the processor. For example, indicating a hardware malfunction.

Question 13

What does the MAR do?

Answer 13

Temporarily holds the address of the memory location (in main memory) that the processor needs to access, either to read from (i.e. load data) or write (i.e. store data) to.

Question 14

What does the Memory Buffer Register/ Memory Data Register do?

Answer 14

It temporarily holds the data (data values or instructions) that are read from or written to the main memory.

Question 15

What does the accumulator do?

Answer 15

Stores the result of any calculation processed by the ALU.
The processor accesses other general purpose registers where temporary values are stored while calculations are completed. Any result resides in the accumulator.

Question 16

What must happen before a fetch decode execute cycle can take place?

Answer 16

The program instructions must have been translated into machine code
The program instructions must have been loaded (from secondary storage) into the main memory (RAM) or provided by the input or output devices by the I/O controllers.

Question 17

What happens during the first part of the Fetch stage?

Answer 17

1) The PC keeps the address of the next instruction to be executed. It’s contents are copied to the MAR, which passes it on to the address bus.
2) The CU then instructs a memory read operation to allow the contents of the memory location to be transferred to the processor. The instruction that is stored there is transferred by the data bus from main memory to the processor and saved in the MBR/MDR.

Question 18

What happens during the second part of the Fetch stage?

Answer 18

3) Simultaneously, the ALU increments the contents of the PC by one to point to the address of the next instruction that needs to be fetched.
4) The contents of the MBR are copied to the CIR, in order to keep the instruction safe so the MBR can be used during the execute stage to store additional data needed.

Question 19

What happens during the Decode stage?

Answer 19

The control unit decodes the instruction kept in the CIR, involving splitting the instruction into operand and opcode to determine:

• what type of instruction needs to be carried out.
• if additional data is required from memory
• where this data is kept in memory

Question 20

What happens during the Execute stage?

Answer 20

The instruction is executed. The exact sequence of operations depends on the type of instruction being executed.
If the program requires a non-sequential instruction to be executed, like if the current instruction is a branch, the address of the next instruction to be executed is determined and loaded to the PC.

Question 21

How does a processor read and write from/to memory?

Answer 21

• If a processor needs to read a memory location, it sends a “read request” via the control bus, along with the address via the address bus. These happen in the same clock cycle.
• Depending on how long it takes to access the memory, the processor then receives the contents via the data bus after a number of clock cycles.
• If a processor needs to write to a memory location, it sends a “write request” via the control bus, along with the data bus containing the data to be stored and the address bus with the memory location address.

Question 22

What is an internal bus?

Answer 22

It is a set of parallel connections allowing internal components to communicate with each other and exchange data.

Question 23

What is an external bus?

Answer 23

It is a set of either series or parallel connections that are used to connect the peripherals to the processor.

Question 24

What is the address bus used for?

Answer 24

The address bus is used to specify the address of a memory location to read data from or write data to.
It is unidirectional.

Question 25

What does the width of the address bus signify?

Answer 25

The width of the address bus refers to the number of parallel lines. It determines the maximum number of addressable memory locations, therefore the maximum memory capacity of a computer system. (called the address space).

Question 26

What is the data bus used for?

Answer 26

The data bus is used to transfer data and instructions to and from the processor and the other units of a computer system. The data bus is bidirectional, i.e. it allows a two-way connection between components of a system — allowing values to be written to or read from a location.

Question 27

What does the width of the data bus signify?

Answer 27

The width of the data bus refers to its number of parallel lines. It determines the number of bits that can be transferred in one operation.

Question 28

What is the control bus used for?

Answer 28

The control bus is used to send control signals that manage and orchestrate the operations of a system. It is bidirectional.

Question 29

What types of control signals does the control bus transmit?

Answer 29

It transmits status signals between the components, and clock signals required to coordinate operations.

Question 30

What is the processor?

Answer 30

The processor, sometimes referred to as the CPU (central processing unit), is the part of the computer that processes data by executing the instructions of stored programs.

Question 31

How do cores impact processing speed generally?

Answer 31

Generally, the more cores a computer has, the more instructions it can execute simultaneously.

Question 32

Why is the rate of processing not directly proportional to the number of cores? (2 reasons)

Answer 32

1 - The computer system needs to spend time organising which tasks get sent to which core.
2 - The nature of the required task might not be such that parallel processing can be used.

Question 33

What is a cache?

Answer 33

A cache is a fast, relatively small capacity set of locations that sit close to the processor; it is used to store the instructions and data most frequently used.

Question 34

How is cache used?

Answer 34

A system constantly swaps data between cache and RAM when running programs. When an instruction is frequently used, it is costly to fetch it from RAM. So, cache memory is used to store instructions that are more likely to be called upon.

Question 35

What happens to cached memory when power is removed?

Answer 35

It is erased, like RAM.

Question 36

What are the differences between cache and RAM?

Answer 36

Cache capacities are far smaller than RAM capacities (measured in MB compared to GB)
Cache memory is faster
Cache memory can’t easily be upgraded or replaced.
Cache memory is more expensive.

Question 37

What is the L1 cache?

Answer 37

This is the smallest and fastest cache, being part of the circuitry of each core. A quad-core CPU has four L1 caches.

Question 38

What is the L2 cache?

Answer 38

L2 cache is shared by cores. It is slower than L1 and often larger. In newer systems, the L2 is similarly part of the core.

Question 39

What is the L3 cache?

Answer 39

L3 cache is slower than L2 cache but larger. It sits on the processor or near it on the motherboard.

Question 40

How does cache memory impact system performance?

Answer 40

The larger the cache, the more instructions can be queued and carried out.
Storing instructions in cache reduces the amount of time it takes to access that instruction and pass it to a CPU core.
If a system does not use caching, then there is an increased need for accessing the main memory, thereby increasing the time it takes for an operation to be carried out.

Question 41

Why is the cache location also important?

Answer 41

Having L2 cache as part of the core circuitry reduces the time for instructions and data to pass through system registers, increasing processing speed.
The more cache levels close to the processor, the more data held near the CPU.

Question 42

What is clock speed commonly described as?

Answer 42

A theoretical maximum. This is because the processing of a single instruction takes more than one clock cycle normally, so a clock speed of 3.6GHz doesn’t mean 3.6 billion instructions will be carried out.

Question 43

What is pipelining?

Answer 43

Pipelining is a technique that improves performance, based on the same principle as an assembly line. In order to apply it, the task needs to be broken down into subtasks that can be handled independently.

Question 44

How can pipelining be used in the Fetch - Decode - Execute cycle?

Answer 44

The fde cycle has a number of distinct stages repeated for every instruction. And between these stages there are registers to keep intermediate results and a clock signal to synchronise the flow of the data.
So, when one instruction is being executed, another one can be decoded and another fetched.

Question 45

Why is pipelining good?

Answer 45

Pipelining avoids keeping internal components idle and means instructions are executed at a faster rate.

Question 46

What is the main negative of pipelining?

Answer 46

It isn’t always possible to predict what needs to be fetched and decoded next, e.g in the case of a branch. In this case, we must “flush the pipes” of the existing instructions.

Question 47

What is the concept of the Von Neumann architecture?

Answer 47

In the 1940s, John von Neumann developed the concept of the stored program computer. It uses the idea of storing instructions and data in main memory and moving them between memory and the processor.

Question 48

What does the Von Neumann architecture consist of?

Answer 48

A processor
A memory unit that can communicate with the processor.
Connections for I/O devices.
Secondary storage for saving/backing up data.

Question 49

How does the Von Neumann processor access the main memory?

Answer 49

It uses the same address and data buses for instructions and data between main memory and the processor, and a control bus to synchronise and control operations.

Question 50

What is the Harvard architecture?

Answer 50

Harvard architecture keeps instructions and data in separate memories, using separate data and address buses to access them.

Question 51

Where is the Harvard architecture often used?

Answer 51

It is often used in embedded systems and microcontrollers, like digital signal processing systems.
This is because it can be specifically adapted to a set of operations and can have very fast speed of operation.

Question 52

Why is Harvard architecture better than Von Neumann?(buses)

Answer 52

Both memories can be accessed simultaneously, meaning the processor will not be kept waiting while loading or saving data to memory. Whereas, in Von Neumann both instructions and data are accessed using the same pathways, which could lead to bottlenecks.

Question 53

Why is Harvard architecture better than Von Neumann? (memory)

Answer 53

With Harvard, the different memories can be adapted to be different sizes, word lengths or even technologies. E.g the instruction memory can be ROM to prevent hacking.
Von Neumann can be exploited by hackers who could disguise malware as data that the processor may accidentally execute when trying to read.

Question 54

Why is Von Neumann better than Harvard?

Answer 54

It enables a more flexible use of main memory, allowing the processor to run more programs not know in advance.
So, it is commonly used in general purpose machines that accommodate the varying needs of the users.