1.1.1 - Structure and function of a processor Flashcards
What is the fetch-decode-execute cycle?
The sequence of operations invovoled in executing an instruction
Name all five special purpose registers that are involved in the instructions process
Accumlator Memory Address register Program count Memory buffer register Current intstruction register
Explain the process of the fetch phase
- The address of the next instruction is copied from the program count to the memory address register
- The instruction held at that address is copied to the memory data register. Simultaneously, the program count is incremented so that it hiolds the address of the next instruction.
- The contents of the Memory data register are copied to the CIR
Explain the process of the Decode and execute phase
The instruction held in CIR is decoded. The instruction is split into OPCODE and OPERAND. The OPCODE is used to determine the type of instruction and what hardware to use to execute it.
The OPERAND holds either The address of the data to be used ith the operation
The actual data to be operated on - which may then be passed to the ALU/Accumulator.
The appropriate instrucrtion is then carried out on the OPERAND.
What is pipelining?
A technique used by some processors to improve performance.
Normally, the steps in the fetch-decode-execute cycle take place one after another. While the next instruction is being fetched, the ALU is idle.
Pipelining allows the next instructions to be fetched at the same time as the processor is performing aithmtic or logical operations, holding them in a buffer close to the processor until the instruction can be performed.
What is the arithmetic and instruction pipeline?
Instruction pipeline consists of stages in which instructions are moved therough the processor, including it being fetched, buffered and then executed.
The arithmetic pipeline represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed.
What is Von Neumann architecture?
The von Nuemann Architecture specifies the basic components of the computer and processor in which a shared memory and bus is used for both data and instructions.
A single data bus is used to transfer both data and instructions.
A single address bus is used to transfer the addresses of data and instructions.
What is the stored program concept?
“Machine code instructions are fetched and executed serially by a processor that performs arithmetic and logical operations.”
A program must be resident in main memory to be executed.
Machine code instructions are fetched from memory one at a time, decoded and then executed within the processor.
What is Harvard architecture?
A computer architecture that has physically seperate memory locations for instructions and data.
Parallel data and instruction buses (An address, data and control bus for each memory) may be used
Often faster than von Neumann as instructions and data can be accessed parallel.
The two different memories can hav diferent characteristics such as the instruction memory may be read-only.
Mostly used in Digital signal processing - eg audio and speech signal processing, sonar and radar, biomedical, seismic data processing or digital image processing.
What is contomperary processor architecture?
A processor that incorporates both aspects of harvard and von Neumann architecture.
In one design, there is one main memory for holding both data and instructions,. but CPU cache memory is divided into instruction cache and a data cache. Harvard architecture is used as the CPU accesses the cache.
