1.1.1 Computer Components

Question 1

CPU

Answer 1

Central Processing Unit
Interprets, executes and processes instructions by manipulating information sent to its registers.

Question 2

CU

Answer 2

Control Unit
Controls how data moves through the CPU by controlling buses
Controls and monitors the flow of data between the CPU and other components
Fetches, interprets and executes each instruction in turn (FDE)

Question 3

ALU

Answer 3

Arithmetic Logic Unit
Performs arithmetic operations (addition etc) and logic operations (comparisons etc)
Can be stored anywhere in memory, but typically the accumulator

Question 4

Buses

Answer 4

A collection of wires that carry data/instructions from one place to another inside a computer
(Collectively known as a system bus)

Question 5

Data bus

Answer 5

Moves all data between the CPU and main memory (bidirectional)

Question 6

Address bus

Answer 6

Transmits the memory addresses of data/instructions so that they can be retrieved by the CPU and executed

Question 7

Control bus

Answer 7

Carries the signal that regulates data flow around a system and is concerned with timing operations like memory writing/reading and I/O operations

Question 8

Clock

Answer 8

Regulates all instructions that take place by simulating pulses of high voltage, representing each cycle that implements an instruction

Question 9

Register

Answer 9

Type of memory in the CPU that holds temporary data while the software program runs (faster than cache)

Question 10

PC

Answer 10

Program Counter
Stores the location in main memory of the next instruction to be executed (either next instruction in sequence or the address to jump to if the current instruction is a branch)
Increments per instruction

Question 11

MAR

Answer 11

Memory Address Register
Stores the address of the next data/instruction to be fetched from RAM
or which data is to be written

Question 12

MDR

Answer 12

Memory Data Register
Temporarily stores data being read from/written to RAM or the instruction fetched from RAM

Question 13

CIR

Answer 13

Current Instruction Register
Stores the instruction currently being executed

Question 14

Accumulator

Answer 14

Stores the result of the ALU’s calculations

Question 15

FDE

Answer 15

The CU in the processor manages the execution of instructions
Each instruction is fetched in sequence, decodes and synchronizes it before executing (by sending control signals)

Question 16

Fetch meaning

Answer 16

Responsible for getting an instruction or data from main memory into the CPU and storing them in its own temp registers

Question 17

Fetch instruction sequence

Answer 17

• The PC is checked (holds the address of the next instruction)
• Address is copied to the MAR
• Address is sent down the address bus to the RAM, and waits for a signal (via control bus)
• A signal is sent by the CU to RAM
• Contents in memory at that address are sent along the data bus to the MDR
• This data is copied from the MDR to the CIR (successful fetch)
• The PC increments

Question 18

Decode sequence

Answer 18

• the data in the CIR is decoded by the decode unit
• made up via opcode and operand
• opcode - what to do, operand - what to do to

Question 19

Execute sequence

Answer 19

(changes for instruction)
- send address x to MAR, to RAM, via address bus
- the CU sends a (e.g. read) signal along control bus to RAM
- contents at memory x are sent to the MDR via data bus
- does whatever (e.g. load to ACC)
- cycle repeats unless it is a stop instruction

Question 20

LMC add

Answer 20

ADD 1xx
Adds value in register xx to the value in the ACC
(<999)

Question 21

LMC subtract

Answer 21

SUB 2xx
Subtracts value in register x from the value in the ACC
A negative flag is set if negative so that BRZ and BRP can test

Question 22

LMC store

Answer 22

STA 3xx
Stores/overwrites value in acc to register xx
ACC doesn’t change

Question 23

LMC load

Answer 23

LDA 5xx
Loads/overwrites value in register xx to ACC
Register xx doesn’t change

Question 24

LMC branch always

Answer 24

BRA 6xx
Unconditional branch
PC loads with xx and points to next instruction to be executed

Question 25

LMC branch if zero

Answer 25

BRZ 7xx If accumulator holds 000, value xx is loaded into the PC to branch to

Question 26

LMC branch if positive

Answer 26

BRP 8xx If accumulator is positive (or negative flag isn't set), then xx is loaded into PC to branch to

Question 27

LMC input

Answer 27

INP 901 go to inbox and copy value into ACC

Question 28

LMC output

Answer 28

OUT 902 Copy acc value into outbox

Question 29

LMC halt

Answer 29

HLT 000 program stops/ends

Question 30

LMC data location

Answer 30

Loads data into next available register or declares variables E.g. AGE DAT 14 stores 14 in variable called AGE, at the next available register

Question 31

Cores

Answer 31

A complete processing unit in the CPU

Question 32

Multitasking

Answer 32

Ability to carry out more than one task at the same time, simultaneously

Question 33

Parallel processing

Answer 33

When a single task is split into parts and processed at the same time

Question 34

Cache

Answer 34

Temporary storage of data and instructions to be read to and written from Located in or on the CPU Larger cache is more expensive but accesses data faster than from RAM

Question 35

Von Neumann Architecture

Answer 35

Shared memory space for programs and data A single control unit processes one instruction at a time following the FDE cyc;e Registers are used as fast access to instructions and data Most computers are built with this All in the same format

Question 36

Harvard

Answer 36

Split into separate memory units which each have their own bus Reading and writing can be done at the same time as fetching Mostly used by RISC processors

Question 37

SIMD

Answer 37

Single Instruction Multiple Data Uses parallel processing where a processor carries out a single instruction on multiple data items simultaneously

Question 38

MIMD

Answer 38

Multiple Instruction Multiple Data Where multiple instructions are carried on multiple data items across several cores

Question 39

Distributed computing

Answer 39

Where multiple computers on a shared network take part of a bigger problem

Question 40

CISC

Answer 40

Complex Instruction Set Computer A large instruction set with more complex instructions Takes more than one clock cycle to execute Cant pipeline Has more general-purpose registers Instructions take less space in memory Laptops + desktops

Question 41

RISC

Answer 41

Reduced Instruction Set Computer Smaller instruction set with more simple instructions Takes one clock cycle to execute Compilers are more complicated therefore generate more instructions Can pipeline Cheaper to manufacture

Question 42

GPU

Answer 42

Graphics Processing Unit Responsible for processing large blocks of visual data, very quickly Slower than standard CPUs GPU's are highly specialised and superior in speed + efficiency Excel at simple operations on large tasks (SIMD)

Question 43

other gpu purposes

Answer 43

oil exploration weather modelling linear algebra

Question 44

multicore system

Answer 44

A multicore processor is a single chip containing two or more independent processing units Each core can FDE its own instructions

Question 45

CMP

Answer 45

Chip Multiprocessor Integrates multiple cores into a single physical chip e.g. two cores is dual core

Question 46

impacts on multicore processors

Answer 46

on-chip shared cache inter-core communication overheads with this communication some programs cannot make maximum use of all cores

Question 47

Parallel processor

Answer 47

The processing of program instructions by dividing them between multiple processors or processing cores