1.1.1

Question 1

What is the role of the control unit?

Answer 1

• Decodes instructions
• Sends and receives control signals from other components.
• Ensures the execution of instructions in the correct sequence.
• Receives a signal from the clock that is used to synchronise operations.
• Connected to all components.

Question 2

What is the role of the ALU?

Answer 2

• Arithmetic and logical bitwise operations.
• Comparisons and binary shifting.

Question 3

What is the role of the program counter?

Answer 3

• Holds the address of the next instruction to be executed.

Question 4

What is a register?

Answer 4

• A location of very high speed memory within the processor.

Question 5

What is the role of the CIR?

Answer 5

• Holds the instruction that the processor is currently executing

Question 6

What is the role of the MAR?

Answer 6

• Holds the address of the memory location that the processor needs to access.

Question 7

What is the role of the MDR/MBR?

Answer 7

• Holds the data that are read from or written to main memory.

Question 8

What is the role of the accumulator?

Answer 8

• Stores the result of any calculation processed by the ALU.

Question 9

What is the data bus?

Answer 9

• Bidirectional bus used for sending data .

Question 10

What is the address bus?

Answer 10

• Unidirectional bus used for sending memory addresses.

Question 11

What is the control bus?

Answer 11

• Unidirectional bus used for sending control signals.

Question 12

What is the role of the clock?

Answer 12

• Maintains the synchronisation of the components.
• Keeps track of current date and time.

Question 13

What is the cache and its role?

Answer 13

• A type of volatile memory that stores small amounts of frequently used data and instructions.
• Reduces amount of time taken to fetch data as it is faster to access and it is closer to the CPU.

Question 14

What happens in the fetch stage?

Answer 14

• Address stored in PC is copied to MAR (AB).
• PC increments to the address of the next instruction (AB).
• Control unit instructs a memory read to allow the contents of the memory location to be transferred to the MDR (DB).
• Instruction in the MDR is copied to the CIR in order to free the MDR for the execute stage (DB).

Question 15

What happens in the decode stage?

Answer 15

• Control unit decodes the instruction kept in the CIR.
• Splits the instruction into operand and opcode to determine the type of instruction.
• Control unit generates specific control signals based on decoded instruction.

Question 16

What happens in the execute stage?

Answer 16

• Instruction is executed by the ALU.
• Result is either stored in the accumulator, buffer register or main memory.

Question 17

What is a core and what is its affect on CPU performance?

Answer 17

• A core a single complete processing unit that can execute.
• Generally more cores = more instructions / cycle.
• However only applications designed for parallel processing can take advantage of multiple cores.
• It takes time to communicate between cores.

Question 18

What is clock speed?

Answer 18

• The maximum number of cycles that the CPU can perform within a second.

Question 19

What is word length/size?

Answer 19

• The amount of data that can be handled at one time by the processor.
• i.e. the number of bits that can be transferred from main memory to the CPU at one time.
• Width of data bus = word length.

Question 20

What is bus width?

Answer 20

• The number of bits that can be transferred by the bus at one time.
• For the data bus, this is usually equal to the word length.
• For the address bus, this determines the number of bits that can be used to form an address.

Question 21

What is parallel processing and how does it work?

Answer 21

• Multiple cores each independently running processes increase the speed of an application.
• This is done by breaking the application down into threads which are executed on separate cores.
• Only applications designed for parallel processing can take advantage of multiple cores.

Question 22

What is pipelining?

Answer 22

• Rather than a component staying idle after it has completed its job in the current cycle, the processor loads that component with the instruction for the next cycle.
• This maximizes CPU efficiency as no component stays idle.
• If the application branches and there is an unexpected instruction that needs to be executed, the pipeline is flushed.
• An application with many branches would not be suitable for pipelining.

Question 23

What are the differences between von Neuman and Harvard architecture?

Answer 23

• VN has a single memory unit whereas H has separate memory units for data and instructions.
• H has separate buses for data and instructions whereas VN only has one bus for both.
• H is commonly used for embedded systems as applications are hardcoded with a fixed size whereas VN is more suitable for a PC where memory can be dynamically allocated.