1.1.1

Question 1

ALU

Answer 1

arithmetic and logic unit - “problem solver” part of the processor that performs arithmetic, logical and shift operations on data - temporarily stores results in the ACC

Question 2

CU

Answer 2

control unit - coordinates the data flow of all the components of the processor - Decodes instructions - Controls buses

Question 3

PC

Answer 3

needed to store the address of the next instruction (to be processed) - Value is then sent to the MAR - After sending the value the PC is incremented / changed to address held in CIR if the operation is a Jump

Question 4

ACC

Answer 4

Temporary storage for data being processed / during calculations used as a buffer

Question 5

MAR

Answer 5

Memory Address Register - Contains the address of the instruction (to be accessed in memory) sent from PC - Contains the address of the data (to be accessed in memory) sent from CIR

Question 6

MDR

Answer 6

Memory Data Register - Contains the instruction which has been accessed from memory - Contains the data which has been accessed from memory - That is referenced by the MAR / Instruction sent to CIR - acts as a buffer

Question 7

CIR

Answer 7

Current Instruction Register - holds current instruction split into opcode + operand

Question 8

Registers

5 register in the CPU

Answer 8

PC
ACC
MAR
MDR
CIR

Question 9

buses

3 types and definition

Answer 9

data
address
control
a series of connectors that transfer signals between internal components - The system bus consists of 3 separate buses carrying Control Signals

Question 10

3 Factors affecting CPU performance

Answer 10

Clock speed
Number of cores
Amount/type of cache

Question 11

clock speed affects on CPU

Answer 11

only 1 FDE cycle is executed per clock ‘pulse’ - faster clock faster execution - too fast and your computer will not work

Question 12

number of cores affects on CPU

Answer 12

Use multiple processor cores at the same time each one working on different parts BUT some instructions are processed sequentially SO it’s not always possible

Question 13

amount / type of cache affects on CPU

Answer 13

it is super fast but very expensive

Question 14

control bus

Answer 14

transmits control signals from the CU to other components of the processor

Question 15

address bus

Answer 15

carries the location address (register) where the data is going (to or from)

Question 16

data bus

Answer 16

bi-directional - carries the data (from one place to another)

Question 17

pipelining

Answer 17

a technique used to improve performance by overlapping stages in the f-d-e or breaking down stages in an arithmetic instruction - Reduces latency because CPU is not idle while waiting for next instruction - All parts of the CPU can be used at once

P1 = F D E F
P2 = D E F D
P3 = E F D E

Question 18

von neueman architecture

Answer 18

Shared memory space for instructions & data
Instructions and data are stored in the same format
A single CU or processor follows a linear fde cycle
One instruction at a time
Registers are used as fast access to instructions/data

Question 19

harvard architecture

Answer 19

Instructions and data stored in separate memory units
Each has its own bus
Reading and writing data can be done at the same time as fetching an instruction
Used by RISC processors

Question 20

contemporary architecture

Answer 20

SIMD - Single Instruction Multiple Data
Parallel processing is where a processor carries out a single instruction on multiple data items at the same time – often used by graphic processors
MIMD - Multiple Instructions Multiple Data
Another version where multiple instructions are carried on multiple data items across several cores
Distributed computing
Where multiple computers on a shared network each take on part of a bigger problem – this can be done on a grand scale over the internet

Question 21

FDE

Answer 21

Fetch Decode Execute cycle - carries out all program instructions The process is repeated for every instruction

Question 22

FDE - Fetch

Answer 22

The address of the next instruction is copied from the PC to the MAR
The instruction held at that address is copied to the MDR
Simultaneously, the contents of the PC are incremented
The contents of the MDR are copied to the CIR

Question 23

FDE - Decode

Answer 23

The instruction held in the CIR is decoded
Split into “operand” & “opcode” additional data (if required) is fetched from memory
And passed to the acc and with the instruction in the CIR, the CU can work out what needs to be done to carry it out

Question 24

FDE - Execute

Answer 24

The instruction is executed and the result held in accumulator or stored in memory

Question 25

CPU

Answer 25

The ‘brains’ of a computer responsible for the FDE cycle has different components that each have a role to do