1.1 The characteristics of contemporary processors, input, output and storage devices Flashcards
1.1.1 structure and function of the processor
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what does the arithmetic and logic unit do
The ALU completes all the arithmetical and logical operations
what is the control unit
the control unit is a part of the processor which directs operations inside the CPU
what are registers
small memory cells that operate at high speeds
what does the program counter (PC) do
the program counter holds the address of the next instruction
what does the memory address register (MAR) do
holds the address of a location that is to be read from or written to
what does the memory data register (MDR) do
Temporarily stores data that has been read
or data that needs to be written
what does the current instruction register (CIR) do
Holds the current instruction being
executed, divided up into operand and
opcode.
what is a bus
a set of parallel wires which connect two or more components together
what is the data bus
a two-way bus used to transport data and instructions between components
what is the control bus
a two-way bus used to transmit control signals between internal and external components.
what is the address bus used for
used to transmit the memory addresses specifying where data is to be sent to or retrieved from
what is von neumann architecture
architecture in which there is a single shared memory and shared data bus for both data and instructions
advantages of von neumann architecture
-Cheaper to develop as the control unit is
easier to design
-Programs can be optimised in size
what is harvard architecture
architecture in which there are two seperate memory and data buses for data and instructions
advantages of harvard architecture
-Quicker execution as data and instructions
can be fetched in parallel
-Memories can be different sizes, which can
make more efficient use of space
contemporary processor
Contemporary processors use a combination of Harvard and Von Neumann architecture.
Von Neumann is used when working with data and instructions in main memory, but uses
Harvard architecture to divide the cache into instruction cache and data cache.
