1.1 The characteristics of contemporary processors, input, output, and storage devices Flashcards

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1
Q

control unit

A

part of processor that controls activity of all other components

. directs flow of data between CPU and other devices
. carries out next instruction
. sends memory read and write requests to main memory on control bus and other command and control signals
. makes extensive use of the status registers and clock
. coordinates and communicates with all parts of the CPU

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2
Q

Buses

A

consists of a series of connectors that transfer signals between internal components. consists of 8,16,32,64 lines

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3
Q

system bus

A

consists of three separate buses carrying control signals, addresses and data

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4
Q

control signals include:

A

memory read
memory write
bus request
bus grant
clock

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5
Q

Memory read

A

causes data from the addressed location in RAM to be placed in a data bus

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6
Q

Memory write

A

causes data on data bus to be written into the addressed location in RAM

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7
Q

Bus request

A

indicates that a device is requesting use of data bus

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8
Q

Bus grant

A

shows CPU has granted access to the data bus

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9
Q

Clock

A

Used to synchronise operations

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10
Q

Arithmetic logic unit (ALU)

A

the problem solving part of the processor. Performs arithmetic, logical and shift operations on data

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11
Q

Program counter (PC)

A

holds the address of the next instruction to be executed

. could be next instruction in a sequence
. could be address to jump or branch - this would be copied from CIR

Has a very close relationship with the MAR. at the start of new FDE cycle the address held in PC is copied to MAR

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12
Q

Memory address register (MAR)

A

holds the address memory location from where data or an instruction is to be fetched or where data is to be written

sends these address to memory down the address bus

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13
Q

Memory data register (MDR)

A

used to temporarily store the data which is read from, or written to memory

can be knows as memory buffer register (MBR) and nicknamed gateway to the processor

all data to and from memory must travel down data bus and pass through the MDR

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14
Q

current instruction register (CIR)

A

holds current instruction being carried out

contents of MDR are copied to CIR if it’s an instruction

contains opcode and operand of current instruction

instruction = opcode + operand

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15
Q

Accumulator

A

One of the general-purpose registers that a CPU has

Stores data and control information

Results of calculations carried by ALU can be stored here

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16
Q

Address bus (unidirectional)

A

carries from CPU to main memory

carries memory addresses that
identify where data is being read from or written to

17
Q

Data bus (bidirectional)

A

carries the binary numbers that make up the actual info being transmitted around CPU

18
Q

Control bus (bidirectional)

A

carries commands and control signals to and from everywhere in the CPU

19
Q

Computer

A

something that takes an input processes the data and produces and output

20
Q

FDE cycle - Fetch

A

PC is checked for next instruction address

Address is copied in MAR

sent along address bus to main memory and waits for control bus

Control unit sends read signal along control bus to main memory

Contents stored in address can be sent to MDR along data bus

Data received by MDR gets copied to CIR

21
Q

FDE - Decode

A

Instruction in CIR is decided by decode unit

instruction is 2 parts opcode and operand
opcode - what to do
operand - what to do it to

operand can contain actual data or the address

decode instruction and see which operation is needed

22
Q

FDE - Execute

A

send address to MAR

send address on address bus to main memory

contents stored in address is sent along data bus to MDR

contents of MDR is copied to accumulator

instruction now complete