1.1 (PROCESSORS) Flashcards
What is a register?
Temporary memory locations in the CPU which are used for a single specific purpose
Name the registers(5)
PC, ACC, MAR, MDR, CIR
What is the purpose of the CPU?
The purpose of the CPU is to fetch, decode and execute instructions. (For processing all data within the system)
What does the ALU do?
Performs any mathematical or decision making calculations
What does the CU do?
Controls data transfer in the CPU and decodes data/instructions.
What does the PC do?
Stores the memory address of the next data/instruction to be fetched
What does the ACC do?
Where values are temporarily stored, either after they’ve been inputted or loaded or after being calculated in the ALU
What does the MAR do?
Where adresses are stored, either being fetched or stored
What does the MDR do?
Where adresses are stored, either being fetched or stored
What does the CIR do?
When an instruction has been fetched from memory it is loaded here before being split into opcode and operand. After this, it will be decoded.
Components of the ALU: (5)
Arithmetic circuit:
This carries out any arithmetic (addition, subtraction, multiplication or division)
Logic circuit:
Carries out operations like AND, OR, NOT, XOR
Registers:
Additional registers to store data
Status flags:
This includes overflow flags (if the value is too large for the register) or could include a zero flag (to tell if the answer is 0 easily)
Busses:
Data transport
What are the 3 busses that connect the CPU and the RAM and their uses?
Data bus:
Holds data being sent to and from the CPU and RAM
Address bus:
Holds addresses sent to and from the CPU and RAM
Control bus:
Sends signals to determine whether theother busses are in read or write mode
What are the operations the 3 busses that connect the CPU and the RAM can do?
Data bus:
Read/Write
Address bus:
Read/Write
Control bus:
Sends signals
FDE cycle?
Fetch
The PC is loaded with O
The value from the PC (0) is copied to the MAR
The data from the MAR (O) is sent across the address bus with the instruction
to read the data sent across the control bus
The data from that location in memory (0) is sent down the data bus to
the MDR
The PC is incremented by 1
Decode
The data is sent from the MDR to the CIR where it is split into the opcode and
operand
This is sent to the CU to be decoded
Execute
Which registers are used here will depend on the instruction being executed
If a value is being inputted (INP) the ACC will store the value
If a value is being outputted (OUT) this will be the value currently in
the ACC
If a value is loaded from RAM (LDA) this will be sent across the data bus
from RAM (in the address location in the MAR) to the MDR
If a value is to be stored (STA) it will take the value from the ACC, send it to
the MDR and then send it across the data bus to RAM (to the address
location in the MAR)
If a value is being added to or subtracted from another value (ADD/SUB)
If the LMC code is to branch (BRA/BRZ/BRP) the comparison will take
place in the ALU
3 ways to measure CPU performance and description:
Clock speed:
Measure of how many state changes the CPU performs per second. One state change can be one or more FDE cycles
Cores:
Number of cores (processors) allowing for more simultaneous tasks
(speed also partially determined by the tasks being performed as some tasks cant be split between multiple processors)
Cache:
Cache stores frequently used data and instructions
It is used as it’s closer to the CPU than RAM and therefore is faster to retrieve data
from (some of the cache is included within each core)
The more cache there is, the more data can be stored which speeds up the performance of the CPU
Explain cache levels
Level 1:
Small and fast, 1 for each core
Level 2:
Shared between cores, slower and has higher capacity than L1
Level 3:
Slower and has larger capacity than L2
Sits on motherboard unlike L1 and L2
What is Pipelining?
Pipelining is the process of carrying out multiple instructions concurrently
Each instruction will be at a different stage of the fetch-decode-execute cycle
One instruction can be fetched while the previous one is being decoded and the
one before is being executed
In the case of a branch, the pipeline is flushed
How does pipelining help?
Pipelining reduces latency
The CPU is not idle while waiting for the next instruction which increases the speed of execution
Differences between the 2 main types of computer architecture:
Memory organisation:
Von Neumann:Unified
Harvard: Separate data and instruction memory
Busses:
Von Neumann: Data, instruction and control busses but the same bus. All the same word size
Harvard: Different busses for data and instructions. Can be different word sizes
CUs:
Von Neumann: Single
Harvard: Seperate
Usage:
Von Neumann: Most modern computers, microcontrollers
Harvard: Specialised embedded systems
How does Harvard architecture perform better than Von Neumann architecture
Two separate areas of memory:
One for instructions and one for data
Instructions and data can be accessed concurrently
Different sets of buses:
One for instructions and one for data
Instructions and data can be accessed concurrently
Pipelining:
Whilst an instruction is being executed the next can be decoded and the subsequent one fetched
Virtual cores / Hyper-threading:
Where one core can act as multiple
Onboard Graphics:
Built-in circuitry for graphical processing
Out of Order Execution:
Instructions can be executed before earlier ones if they are ready
Super Scalar:
Multiple instructions can be executed simoulatiously
