1.1 Components of a computer and their uses Flashcards
1.1.1 (a) CU
Control Unit
Coordinates all activities of the CPU (Communicates with all parts of the CPU)
Directs the flow of data between the CPU and other devices
Accepts the next instruction, decodes and handles execution and stores the data in memory or registers
Sends memory read/write requests to main memory on the control bus: As well as other command/control signals
Bus and interrupts requests/grants
Uses the SRs and the Clock
1.1.1 (a) PC
Program Counter: Register
Holds the address of the next instruction to be executed (in a sequence of instructions)
Increments after each instruction in a sequence
Holds the address to jump to if there is a branch or jump command
Linked with the MAR: Data is copied from the PC into the MAR
1.1.1 (a) MAR
Memory Address Register
Hold the address of the memory location w=from which data/instructions are to be fetched from/written to
Uses the address bus
1.1.1 (a) MDR/MBR
Memory Data/Buffer Register
Temporarily Stores Data which is read from/ written to memory
All data to/ from memory passes through the data bus and MDR
1.1.1 (a) CIR
Current Instruction Register
Holds the current instruction being executed
Contents of the MDR are copied into the CIR (If the MRD contains an instruction)
Contains the Opcode and the Operand
1.1.1 (a) ALU
Arithmetic Logic Unit
Preforms Arithmetic and Logical Operations on Data
Operations of Numbers: ADD, SUBTRACT, MULTIPLY, DIVIDE
Also preforms Bitwise Shifts
Boolean Logic: Comparison, AND, OR, NOT, XOR
Makes use of General Purpose Registers to Store Results
1.1.1 (a) ACC
Accumulator: Register
Special Case of General Purpose Register
Stores data/ control information
Linked with the ALU
1.1.1 (a) Buses
Address Bus: Carries memory addresses that correspond to read/write locations in memory (1 directional)
Data Bus: Carries actual information being transmitted around the computer (2 directional)
Control Bus: Carries command and control signals to/from all components, e.g. Read/Write Signals
1.1.1 (b) Fetch
The programs counter is checked as it holds the next address
The address is copied into the MAR
The address is sent along the address bus to main memory, where is waits to receive a control signal.
The CU sends a control signal
MDR takes the result via the data bus and copies it into the CIR
The PC increments
1.1.1 (b) Decode
Preformed by the CU
The data in the CIR is split into the
Opcode: What to do
Operand: What to do it to (address or data)
The CU prepares for the execution stage
1.1.1 (b) Execute
The process is carried out
The process repeats
1.1.1 (b) Branching
If the operand contains a branch, the operand (address to branch to) is copied into the PC
1.1.1 (c) Clock Speed
Measured in Hertz (Hz) number cycles of instructions executed per second
Higher clock speed = Higher performance
Modern Computers use Gigahertz (GHZ) Billions of Cycles per Second
1.1.1 (c) Cache Size
Temporary storage of data and instructions
Being read from/ written to
Stores copies of recent data and instructions
Faster
Limited due to Cost
1.1.1 (c) Number of Cores
Multiple cores can run multiple programs at the same time
Cores communicate, which takes time
The software needs to be able to make use of multicore systems for improved performance
1.1.1 (d) Pipelining
Multiple Instructions are overlapped, to further improve CPU performance.
Different parts of the FDE cycle happen to different instructions simultaneously
Registers are more efficient, as different instructions can be processed at the same time
1.1.1 (d) Instruction Pipeline
The stages that an instruction moves through the processor
1.1.1 (d) Arithmetic Pipeline
Parts of an arithmetic operation that can be broken down and overlapped
1.1.1 (d) Flushing the Pipe
When branching and jumps are occur, the pipeline must be flushed, as lines which are being fetched / decoded are not need, so they must be removed.
Limits benefits of pipelining with a program with lots of branching
1.1.1 (e) Von Neumann Architecture
Shared memory space for data and instructions
Instructions and data are stored in the same format
Single CU/ Processor
Follows a linear FDE cycle
One instruction is processed at a time
Registers are used as fast access to instructions and data
1.1.1 (e) Harvard Architecture
Instructions and data are stored in separate memory units
Instructions and data use separate buses
Reading/ Writing data can be done at the same time as fetching instructions
Used by RISC computers
1.1.1 (e) SIMD
Contemporary Architecture
Single Instruction Multiple Data
Parallel Processing carries out a single instruction on multiple data items at the same time
Used in Graphics Processors
1.1.1 (e) MIMD
Contemporary Architecture
Multiple Instructions Multiple Data
Multiple Instructions are carried out across several cores
1.1.1 (e) Distributed Computing
Contemporary Architecture
Multiple Computers on a shared network sharing resources to tackle a larger problem