1.1 Architecture of the CPU Flashcards
Central processing unit (CPU)
The purpose of the CPU is to fetch decode and execute instructions.
FDE cycle
The FDE cycle is the cycle that the CPU runs billions of times per second. A computer takes an input and then delivers the output for the user.
Fetch stage
The address of the instruction that needs to be processed next is copied from the Program Counter (PC) to the Memory Address Register (MAR).
The PC is incremented to point to the next instruction that will be needed when the cycle starts again.
The instruction stored at the location held by the MAR is copied to the MDR.
Decode stage
The Control Unit decodes the instruction and sends control signals to the component within or outside the CPU that needs to act.
Execute stage
The operation indicated by the instruction is performed by the appropriate component.
Arithmetic logic unit (ALU)
Performs arithmetic operations and logical decisions.
Control unit (CU)
The Control Unit transmits control signals to other components of the CPU.
The Control Unit follows the fetch-decode-execute cycle to execute program instructions.
There are two main components of the Control Unit:
The clock, which coordinates the CPU’s activity.
The decoder, which decodes program instructions.
Cache
Very small, fast memory located in the CPU which is used to provide quick access to frequently used instructions and data.
It is closer to the CPU than RAM therefore faster than RAM.
The more cache there is the more data can be stored which speeds up the performance of the CPU.
It prevents the CPU from having to repeatedly fetch frequently used instructions from RAM.
Registers
Extremely small fast memory located in the CPU. Each register has its own purpose.
PC, MAR, MDR, ACC
Von Neumann architecture
The Von Neumann architecture is a design of the CPU. It outlines how the computer memory, input and output devices and processor all work together. The idea that the programme instruction and the data required are both stored in the same memory.
Program counter (PC)
Holds the memory address of the next instruction to be executed. Increments by 1 as the FDE cycle runs.
Memory address register (MAR)
Holds the memory address of the current instruction to be executed and the address of the data to be fetched.
Memory data register (MDR)
Stores the data or actual instruction which has been fetched from memory.
Accumulator (ACC)
Temporarily stores the result of any calculations that have taken place in the ALU.
