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Question 1

What is the operation of the cpu?

Answer 1

Repeat the fetch cycle, indirect cycle, execute cycle and interrrupt cycle.

Question 2

What does the fetch cycle involve?

Answer 2

1. Copy program counter into memory address register.
2. Attach memory address register to address bus.
3. Control unit issues a READ.
4. Copy the data bus value into the Memory Buffer Register.
5. Copy the value from Memory bus register to Instruction register.
6. add 1 to program counter.

Question 3

What occurs in the indirect cycle?

Answer 3

Indirect addresses are converted into direct addresses.

Question 4

What occurs in the execute cycle?

Answer 4

This varies based on the instruction.

Question 5

What occurs in the interrupt cycle?

Answer 5

Test the IRQ line, pushing PC onto the stack and loading it with the interrupt service routine address if triggered.

Question 6

What is microprogramming?

Answer 6

Microprogramming involves 4 cycles: fetch, indirect, execute, and interrupt. There are 4 microinstruction typeS: Register to Register, input, output, and manipulate(occurs in ALU).
Microprogramming is basically the lowest level operations the CPU can perform, everything else is just combinations of these.

Question 7

What is a horizontal microinstruction?

Answer 7

One which directly selects the registers, ALU operation, and destination in the instruction. Making it a quite large bit pattern. This is the most common due to how cheap transistors are.

Question 8

What is a vertical microinstruction?

Answer 8

All operations sent through demultiplexer to find out location to go to, this takes longer to do but conserves bits.

Question 9

What is instruction pipelining?

Answer 9

Fetch unit pre-fetches the next instruction while execute unit performs current, if a branch occurs(making the prepped instruction wrong) it is discarded and loaded with correct instruction.

Question 10

What are the parts of a 6 stage pipeline?

Answer 10

Fetch instruction, decode instruction, calculate operands, fetch operands, execute instruction, write operand.

Question 11

What are the main problems with pipelines?

Answer 11

Data must be moved through each stage of the pipeline, potentially increasing overall time for each instruction. The extra hardware is also complex.

Question 12

What is CISC?

Answer 12

Complex instruction set computers, in order to utilise the extra transistors they add extra instructions, make the PCU do more and have pipelines.

Question 13

What is the semantic gap?

Answer 13

New instructions added to CPU, but they were not being used by programmers, or compilers

Question 14

What is RISC?

Answer 14

Reduced instruction set computers, these use the extra transistors to increase the number of registers, design the pipeline for conditional branches and make each instruction do less
One instruction is ran per cycle, register to register operations are common, simple address modes and instruction formats.

Question 15

How do RISC register windows work?

Answer 15

Large number of registers addressed relative to a start, out registers of one routine are the “in” registers of next, each routine has local registers, upon entry to a routine the start is moved to the next block.
There will be an arbitrary depth of nesting and arbitrary number of registers in each window, requiring writing to memory if more than this are used.

Question 16

Compare RISC and CISC.

Answer 16

RISC requires more program instructions then CISC but CISC does more per instruction

Question 17

What is a superpipeline?

Answer 17

If the RISC(or micro-coded CISC) instructions are simple enough then we can increase the CPU’s internal clock speed and do each simple operation in less time.

Question 18

What does Superscalar mean and what are some limitations?

Answer 18

Have more than one pipeline, known as instruction-level parallelism. Limitations include: True data dependency(Write after read), output dependency(write after write), Antidependency(Read after write),
Procedural dependency and resource conflicts.

Question 19

What is out-of-order execution? How does it work?

Answer 19

instructions without dependencies don’t have to be executed in a specific order.
The instructions of a program are fetched with branch prediction. The stream is checked for dependencies, Instructions are re-ordered by their dependencies and then executed based on dependencies and hardware resources. Results are recorded or discarded(if speculative prediction occurs).

Question 20

What is hyperthreading?

Answer 20

superscalar architecture with pipelines each with their own part of memory and registers, allowing for multiple programs to execute at once, known as simultaneous multithreading (SMT).

Question 21

How can we reduce CPU heat?

Answer 21

Reduce speed of CPU, the CPU can still function fast if we construct the CPU from multiple processors which share buses and level 2 cache.

Question 22

What is SIMD?

Answer 22

Single instruction multiple data, uses array registers and performs an instruction on each part, this way the instruction decoding only occurs once