1: The CPU Flashcards
CU
- Coordinates all activities of the CPU
- Directs the flow of data between the CPU and other devices
- FDE cycle happens here
- Sends memory read/write signals to main memory on the control bus
PC
- Holds the address of the next instruction to be executed
- Holds a close relationship with MAR: the address held in the PC is copied to the MAR
MAR
-Holds the address of the memory location from which data is to be fetched or to which data is to be written
-Sends addressed to memory down address bus
MDR
- Temporarily stores the data which has been read from or written to memory
- All data to and from memory must pass through the MDR via the data bus.
CIR
- Holds the current instruction being executed
- Contents of MDR are copied into CIR if it is an instruction
- Contains opcode and operands of the current instruction
- Instruction = opcode + operands
ALU
-performs arithmetic and logic functions in the CPU
-ADD, SUBTRACT, MULTIPLY, DIVIDE
- AND, OR, NOT, XOR
- Binary shift
-Comparison
ACC
- a general purpose register which stores results of calculations performed in the ALU as well as control information
- The more general purpose registers a CPU has, the faster it may operate
Address Bus
Carries memory addresses that identify where the data is being read or written to
Data Bus
Carries the binary that make up the actual information being transmitted around the CPU
features of Von Neumann architecture
- Shared memory space for instructions and data
- Instructions and data are stored in the same format
- A single control unit or processor follows a linear FDE cycle
- One instruction at a time
- Registers are used as fast access to instructions and data
Features of Harvard architecture
- Instructions and data stored in separate memory units
- each has its own bus
- Reading and writing data can be done at the same time as fetching an instruction
- Used by RISC processors
How do Von Neumann and Harvard architectures differ from contemporary architectures?
- SIMD (Single Instruction Multiple Data): Parallel processing is where a processor carries out a single instruction on multiple data items at the same time - often used by graphic processors
- MIMD (Multiple Instructions Multiple Data), another version where multiple instructions are carried on multiple data items across several cores
- Distributed computing : Where multiple computers on a shared network each take part on part of a bigger problem
Clock Speed
- measured in hertz (Hz)
- Number of FDE cycles per second
Cache size
- Temporary storage of frequently used data and instructions being read to and written from
- Located on or near the CPU
- Stores copies of recent data and instructions
- Quicker to access than RAM, improving efficiency of CPU
Number of cores
- A core is a complete copy of the CPU, with its own separate registers and units
- CPUs with multiple cores have more power to run multiple programs at the same time
What are registers?
Small memory cells that operate at very high speeds and used to temporarily store data involved in the FDE cycle.
Fetch
- Address from the PC is copied to the MAR
- Instructions held at that address is copied to the MDR by the data bus
- simultaneously the PC is incremented
- The value held in the MDR is copied to the CIR
Decode
- The contents of CIR are split into opcode and operand
Execute
-The opcode is executed on the operand.
ADD
add
SUB
subtract
STA
store
LDA
load
BRA
Branch Always
BRZ
Branch if zero
BRP
Branch if positive
INP
input
OUT
output
Control Bus
Carries command and control signals to and from every other component of the CPU/computer
HLT
End program
DAT
Data Location
What is pipelining?
- The process of completing the fetch, decode and execute cycles of three separate instructions simultaneously
- the appropriate data is held in a buffer in close proximity to the CPU until it is required
- while one instruction is being executed, another can be decoded and another fetched
What is the aim of pipelining?
To reduce the amount of the CPU kept idle
What does instruction pipelining do?
Separate the instruction into fetching, decoding and executing
What does arithmetic pipelining do?
Break down the arithmetic operations and overlapping them as they are performed
