1: The CPU Flashcards

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1
Q

CU

A
  • Coordinates all activities of the CPU
  • Directs the flow of data between the CPU and other devices
  • FDE cycle happens here
  • Sends memory read/write signals to main memory on the control bus
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2
Q

PC

A
  • Holds the address of the next instruction to be executed
  • Holds a close relationship with MAR: the address held in the PC is copied to the MAR
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3
Q

MAR

A

-Holds the address of the memory location from which data is to be fetched or to which data is to be written
-Sends addressed to memory down address bus

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4
Q

MDR

A
  • Temporarily stores the data which has been read from or written to memory
  • All data to and from memory must pass through the MDR via the data bus.
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5
Q

CIR

A
  • Holds the current instruction being executed
  • Contents of MDR are copied into CIR if it is an instruction
  • Contains opcode and operands of the current instruction
  • Instruction = opcode + operands
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6
Q

ALU

A

-performs arithmetic and logic functions in the CPU
-ADD, SUBTRACT, MULTIPLY, DIVIDE
- AND, OR, NOT, XOR
- Binary shift
-Comparison

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7
Q

ACC

A
  • a general purpose register which stores results of calculations performed in the ALU as well as control information
  • The more general purpose registers a CPU has, the faster it may operate
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8
Q

Address Bus

A

Carries memory addresses that identify where the data is being read or written to

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9
Q

Data Bus

A

Carries the binary that make up the actual information being transmitted around the CPU

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10
Q

features of Von Neumann architecture

A
  • Shared memory space for instructions and data
  • Instructions and data are stored in the same format
  • A single control unit or processor follows a linear FDE cycle
  • One instruction at a time
  • Registers are used as fast access to instructions and data
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11
Q

Features of Harvard architecture

A
  • Instructions and data stored in separate memory units
  • each has its own bus
  • Reading and writing data can be done at the same time as fetching an instruction
  • Used by RISC processors
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12
Q

How do Von Neumann and Harvard architectures differ from contemporary architectures?

A
  • SIMD (Single Instruction Multiple Data): Parallel processing is where a processor carries out a single instruction on multiple data items at the same time - often used by graphic processors
  • MIMD (Multiple Instructions Multiple Data), another version where multiple instructions are carried on multiple data items across several cores
  • Distributed computing : Where multiple computers on a shared network each take part on part of a bigger problem
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13
Q

Clock Speed

A
  • measured in hertz (Hz)
  • Number of FDE cycles per second
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14
Q

Cache size

A
  • Temporary storage of frequently used data and instructions being read to and written from
  • Located on or near the CPU
  • Stores copies of recent data and instructions
  • Quicker to access than RAM, improving efficiency of CPU
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15
Q

Number of cores

A
  • A core is a complete copy of the CPU, with its own separate registers and units
  • CPUs with multiple cores have more power to run multiple programs at the same time
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16
Q

What are registers?

A

Small memory cells that operate at very high speeds and used to temporarily store data involved in the FDE cycle.

17
Q

Fetch

A
  • Address from the PC is copied to the MAR
  • Instructions held at that address is copied to the MDR by the data bus
  • simultaneously the PC is incremented
  • The value held in the MDR is copied to the CIR
18
Q

Decode

A
  • The contents of CIR are split into opcode and operand
19
Q

Execute

A

-The opcode is executed on the operand.

20
Q

ADD

A

add

21
Q

SUB

A

subtract

22
Q

STA

A

store

23
Q

LDA

A

load

24
Q

BRA

A

Branch Always

25
Q

BRZ

A

Branch if zero

26
Q

BRP

A

Branch if positive

27
Q

INP

A

input

28
Q

OUT

A

output

29
Q

Control Bus

A

Carries command and control signals to and from every other component of the CPU/computer

30
Q

HLT

A

End program

31
Q

DAT

A

Data Location

32
Q

What is pipelining?

A
  • The process of completing the fetch, decode and execute cycles of three separate instructions simultaneously
  • the appropriate data is held in a buffer in close proximity to the CPU until it is required
  • while one instruction is being executed, another can be decoded and another fetched
33
Q

What is the aim of pipelining?

A

To reduce the amount of the CPU kept idle

34
Q

What does instruction pipelining do?

A

Separate the instruction into fetching, decoding and executing

35
Q

What does arithmetic pipelining do?

A

Break down the arithmetic operations and overlapping them as they are performed