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Computer Science: Components of a Computer > 1. Processor Components > Flashcards

1. Processor Components Flashcards

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1
Q

What are the components of the CPU?

A
  1. Control Unit (CU)
  2. Buses
  3. Arithmetic Logic Unit (ALU)
  4. Dedicated registers
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2
Q

What are the roles of the Control Unit?

A
  1. Controls and co-ordinates the activities of the CPU
  2. Directs flow of data between CPU and other devices
  3. Accepts next instruction
  4. Decodes instruction into several sequential steps
  5. Manages the execution
  6. Stores resulting data in memory or registers
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3
Q

What is a bus?

A

A set of parallel wires connecting two or more components of a computer

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4
Q

Name the 3 buses.

A
  1. Address bus
  2. Data bus
  3. Control bus
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5
Q

How is the processor connected to the main memory?

A

Via the 3 buses

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6
Q

What happens when the CPU wishes to access a particular main memory location?

A
  1. Sends address to memory on address bus
  2. Data in address location returned to CPU on data bus
  3. Control signals sent along control bus
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7
Q

What are the 3 buses called collectively?

A

System bus

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8
Q

What is the role of the address bus?

A

To transmit memory addresses specifying where data is to be sent to or retrieved from

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9
Q

What is the role of the data bus?

A

To transport data and instructions between components

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10
Q

What are the roles of the control bus?

A

To transmit control signals between internal and external components
Co-ordinates use of address and data buses
Provides status information between system components

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11
Q

Is the address bus bi-directional?

A

No

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12
Q

Is the data bus bi-directional?

A

Yes

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13
Q

Is the control bus bi-directional?

A

Yes

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14
Q

Name the 6 control lines.

A
  1. Bus Request
  2. Bus Grant
  3. Memory Write
  4. Memory Read
  5. Interrupt Request
  6. Clock
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15
Q

What does the Bus Request control line do?

A

Indicates that a device is requesting the use of the data bus

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16
Q

What does the Bus Grant control line do?

A

Indicates that the CPU has granted access to the data bus

17
Q

What does the Memory Write control line do?

A

Causes data on the data bus to be written into the addressed location

18
Q

What does the Memory Read control line do?

A

Causes data from the addressed location to be placed on the data bus

19
Q

What does the Interrupt Request control line do?

A

Indicates that a device is requesting access to the CPU

20
Q

What does the Clock control line do?

A

Synchronises operations

21
Q

How is memory divided internally?

A

Into units called words

22
Q

What is a word?

A

A fixed size group of digits

23
Q

What is the ALU used for?

A

Performing arithmetic (+, -, x, /) and logical (e.g. AND, OR, NOT, XOR, binary shifts) operations on data

24
Q

What are registers?

A

Small memory cells that operate at very high speeds

25
Q

What are registers used for?

A

Temporarily storing data

Site of arithmetic, logical and shift operations

26
Q

Name the 5 registers.

A
  1. Program Counter (PC)
  2. Accumulator (ACC)
  3. Memory Address Register (MAR)
  4. Memory Data Register (MDR)
  5. Current Instruction Register (CIR)
27
Q

What is the purpose of the PC register?

A

Holds address of next instruction to be executed

28
Q

What is the purpose of the ACC?

A

Stores results from calculations

29
Q

What is the purpose of the MAR?

A

Holds address of the location to be read from or written to

30
Q

What is the purpose of the MDR?

A

Temporarily stores data that has been read or needs to be written

31
Q

What is the purpose of the CIR?

A

Holds the current instruction being executed, divided into operand and opcode

32
Q

What does the operand contain?

A

The data or address of the data which the operation is to be performed on

33
Q

What does the opcode contain?

A

The type of operation that needs to be executed

34
Q

What is the Fetch-Decode-Execute cycle?

A

Sequence of operations completed to execute an instruction

35
Q

What happens during the Fetch phase?

A
  1. Address from PC is copied to MAR
  2. Instruction held at that address is copied to MDR via data bus
  3. Simultaneously, contents of PC incremented
  4. Value held in MDR is copied to CIR
36
Q

What happens during the Decode phase?

A
  1. Contents of CIR divided into operand and opcode
  2. Operand may contain the following:
    a. address of data to be used (copied to MAR)
    b. actual data to be operated on (copied to MDR)
    c. data to be operated on may be passed to ALU or
    ACC
37
Q

What happens during the Execute phase?

A
  1. Decoded instruction is executed

Computer Science: Components of a Computer (4 decks)

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