1 - Multicore Architecture Concepts Flashcards
MIMD parallelism
a processor that can execute multiple programs on multiple data at the same time
SIMD instructions
some processors have SIMD unit to compute an instruction on multiple data (vectors) in a single instruction
Hardware Multithreading
is the ability of a central processing unit (CPU) (or a single core in a multi-core processor) to provide multiple threads of execution concurrently, supported by the operating system
Fast-level cache
in a cache hierarchy, the cache which is nearest from the CPU is the fastest
False sharing
False sharing occurs when threads on different processors modify variables that reside on the same cache line. This invalidates the cache line and forces an update, which hurts performance.
Heterogeneous multicore system
where a system uses more than one kind of processor or cores
Why does the MSI coherence protocol as described in the lecture, guarantee sequential (memory) consistency?
bonne question
power wall
l higher clock rate ‡ more power, heat problems
sequential memory consistency
the result of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program.
Symmetric multiprocessor (SMP)
est une architecture parallèle qui consiste à multiplier les processeurs identiques au sein d’un ordinateur, de manière à augmenter la puissance de calcul, tout en conservant une unique mémoire.
Bus snooping
is a scheme by which a coherency controller (snooper) in a cache monitors or snoops the bus transactions, and its goal is to maintain a cache coherency in distributed shared memory systems.
Moore’s Law
The number of transistors
per mm2 chip area
doubles approximately
every 2 years
Weak memory consistency (in a shared memory system)
Weak memory consistency is about the semantics of concurrent programs taking into account the effects of: I multicore hardware implementations I and compiler optimizations.
What is the purpose of multi-banked memory?
A multi-bank cache just stripes data into multiple memory module, for example, striping one word (4 bytes) across 4 modules. When you read data from multi-bank cache, you can read it in parallel (read one byte from 4 banks at the same time, instead of 4 bytes from one bank sequentially). The result is that the hit time is reduced.
