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A Level Computer Science > Chapter 1 - components of a computer > Flashcards

Chapter 1 - components of a computer Flashcards

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1
Q

what is the CPU?

A

Central Processing Unit, aka. the processor, is the controlling processor of the computer which executes instructions

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2
Q

what are the 3 main elements of the CPU?

A
  • ALU
  • Control unit
  • Registers
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3
Q

what is the ALU?

A
  • Arithmetic Logic Unit
  • performs arithemetic and logical operations on data - eg. normal arithmetic, shift operations, boolean logic operations by comparing 2 values
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4
Q

What is the control unit?

A
  • controls and coordinates the activities of the CPU, directing the flow of data between the CPU and other devices - makes sure instructions execute correctly
  • accepts next instruction, decodes it into several sequential steps (eg. fetch addresses/data from memory) manages execution + stores resulting data back into memory/registers
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5
Q

what are registers?

A
  • they are special memory cells where a single item of data can be stored
  • very high speed area of the CPU
  • results of all arithmetic, boolean and shift operations are stored in a register - they have to be in one in order to be called upon
  • typically up to 16 general purpose registers in the CPU
  • increasingly being slowed down by the speed of light
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6
Q

what are some typical special registers?

A
  • program counter (PC) - holds the address of the next instruction to be executed (next in sequence or when branched)
  • Memory address register (MAR) - holds the address of the memory location currently in use - data to be fetched from/written in
  • memory data Register (MDR) - temporarily stores data read from or written to memory (aka. memory buffer register)
  • Current Instruction Register (CIR) - holds current instruction being executed (divided into opcode and operand)
  • Accumulator - stores results of calculations processed by CPU, takes the place of general registers
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7
Q

what is a bus?

A

It is a set of parallel wires connecting 2 or more components of a computer to another. It typically consists of 8, 16, 32. or 64 lines

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8
Q

What are the 3 types of bus?

A
  • data bus
  • address bus
  • control bus
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9
Q

what is a data bus?

A

It is a bi-directional path for moving data and instructions between processor components and memory

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10
Q

What is an address bus?

A

every word in memory has its own specific memory address. When data is to be saved to/loaded from memory, the address of the location it needs to be stored in/retrieved from must be sent along the address bus. It is uni-directional.

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11
Q

what is a word?

A

a fixed group of digits, usually 16, 32, or 64 bits, which is handled as a unit by the processor

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12
Q

what is a control bus?

A
  • it is a bi-directional bus that makes sure that access to and use of data and address buses between different components of the system does not lead to conflict.
  • It’s purpose is to transmit command, timing and specific status information between components - basically make sure everything is executed at the right time and order.
  • example control line = Interrupt request, clock
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13
Q

what is the fetch-decode-execute cycle?

A

It is the sequence of operations involved in executing an instruction. It can be divided into 3 phases - fetch, decode and execute

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14
Q

describe the fetch decode execute cycle

A
  1. PC holds the address of the next operation
  2. copy contents of PC into MAR
  3. Increment PC
  4. Load instructions at MAR address into MDR
  5. Copy instructions from MDR to CIR
  6. Decode instructions in CIR (done by control unit) - break down into opcode and operand
  7. Execute instruction
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15
Q

What is opcode?

A

The part of an instruction that determines the type of instruction it is and what hardware to use

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16
Q

what is the operand?

A

the part of the instruction which holds either the address of data to be used in the operation; or actual data to be operated on.

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17
Q

What are some factors affecting processor performance?

A
  • clock speed
  • number of cores/duplicate processors linked together on a single chip
  • amount and type of cache memory
18
Q

How does clock speed affect a processor’s performance?

A
  • lock speed is how many clock cycles a CPU can complete per second
  • clock speed is measured in gigahertz (GHz)
  • average processor clock speed is 2-4 GHz
  • the greater the clock speed, the faster each cycle will be completed, which means more instructions can be executed per second which means instructions will be processed faster making a faster processor
19
Q

What is a clock cycle?

A

A single electronic pulse of the CPU - the time it takes for the system clock to go from 0 to 1 to 0 again. The CPU cannot complete operations faster than the clock cycle.

20
Q

How does the number of processors affect the performance of the CPU?

A
  • dual-core = 2 processors linked together, quad-core = 4 processors linked together
  • Theoretically - each processor can process a different instruction at the same time with its own FDE cycle so a quad-core processor would be 4 times more efficient than a single core processor
  • not always the case - software may not be able to take full advantage of both processors
  • but generally, the more cores, the more instructions running simultaneously which makes a faster processor
21
Q

How does amount and type of memory affect the performance of a processor?

A
  • when an instruction is fetched from main memory it can be stored in the cache so it can be fetched from there if it is needed soon after which is much faster than going back to main memory since it is further away from the CPU than cache
  • as cache fills up, unused instructions/data is replaced with more recent ones

3 levels of cache:
L1 - extremely fast but small - 2-64KB
L2 - fairly fast and medium sized - 256KB-2MB
L3 - only on some CPUs

22
Q

What is cache?

A

A small amount of very expensive, fast memory inside the CPU

23
Q

What is pipelining?

A
  • a technique used by some processors to improve performance
  • computer architecture allows next instruction to be fetched at the same time as the processor is performing arithmetic and logical operations, holding them in a buffer close to the CPU until it can be performed
  • this makes use of how the arithmetic part of the processor is idle when an instruction is being fetched
  • divided into an instruction pipeline and an arithmetic pipeline
  • quite common in PC processors - eg. Intel Pentium uses it to do up to 6 instructions simultaneously
24
Q

What is an instruction pipeline?

A

it is the stages when an instruction is moved through the processor - fetched, buffered, executed

25
Q

what is the arithmetic pipeline?

A

It represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed

26
Q

How does address bus size work?

A
  • when the processor wants something from memory, it puts the address of the desired word on the address bus
  • The width of the address bus determines the maximum possible memory capacity of the system
  • Example - 32-bit address bus = 2^32 memory address locations = 4GiB addressable memory (average in 2016)
27
Q

How does data bus size work?

A
  • the width of the data bus determines the largest operand (address or value) that can be held in a word
  • eg. 16-bit data bus = largest possible integer = 2^16 - 1
28
Q

How is opcode expressed in assembly language?

A

as a mnemonic - eg. ADD, SUB, LDA

29
Q

What is the stored program concept?

A
  • Machine code instructions are fetched and executed serially by a processor that performs arithmetic and logical operations
  • program must be resident in main memory to be executed
  • machine code instructions are fetched from memory one at a time, decoded and executed in the processor
30
Q

What are the key features of the von Neumann machine?

A
  • one shared memory for data + instructions
  • same data bus transfers data + instructions
  • same address bus transfers addresses of data + instructions
  • data + instructions stored in the same format with the same word length
  • one FDE cycle at a time
  • programs can be optimised in size
31
Q

what are the key features of the Harvard architecture?

A
  • has separate memories for data + instructions
  • different memory types may have different characteristics - eg. instructions = read only, data = read/write
  • different memories = different word sizes - eg. some systems have large instruction memories so instructions have large word sizes
  • data + instructions don’t share buses so they can be different sizes - often instruction bus is wider than data bus
  • often faster than von Neumann architecture - data + instructions can be fetched in parallel instead of competing for one bus
  • programs tend to be large
32
Q

When is von Neumann architecture used?

A

in conventional processors in PCs, servers and embedded systems with only control functions

33
Q

When is Harvard architecture used?

A
  • Digital Signal processing - audio + speech processing, sonar + radar signal processing, biomedical signal processions, seismic data processing, digital image processing, etc.
  • embedded systems
34
Q

what is an embedded system?

A

Special purpose computers built into devices (often operating in real time) - eg. in navigation systems, traffic lights, flight control systems and simulators

35
Q

What is contemporary processor architecture?

A
  • it incorporates aspects of von Neumann and Harvard processor architectures
  • eg. one main memory for data + instructions but there is data cache and instruction cache
  • eg. digital signal processors have multiple parallel data buses and 1 instruction bus
36
Q

What is pipelining?

A
  • The concurrent decoding of 2 or more machine instructions
  • when one instruction is executed, a second is being decoded while a 3rd is fetched
  • much more efficient than traditional FDE cycle
  • easier with Harvard architecture - different memories
37
Q

Key features of CISC architecture?

A
  • Complex instruction set computers
  • large instruction set is used to accomplish tasks in as few lines of assembly language as possible - disguises several separate tasks as one line of code
  • older weirdly
  • combines load/store instruction with instruction that does the calculation
  • smaller code size - fewer instructions
  • transistors store complex instructions
  • lots of addressing modes
  • emphasis on hardware
38
Q

What are the advantages and disadvantages of CISC architecture?

A

Advantages:
- compiler has little work to do translating a high level language statement into machine code
- relatively short code = very little RAM required to store instructions + more CPU cycles per second

Disadvantages:
- lots of specialised instructions have to be built into hardware even though only about 20% are normally used
- lots of transistors = more power needed = they’re very power intensive

39
Q

When is CISC architecture used?

A
  • not used much anymore
  • but often found in embedded systems and microcontrollers still
40
Q

Key features of RISC architecture?

A
  • Reduced instruction set computer
  • emphasis on software
  • uses a much smaller set of instructions, each taking one FDE cycle - complex tasks are done using lots of simple instructions
  • more transistors for memory registers
  • pipelining is possible because each instruction takes one clock cycle
  • made after CISC
  • larger program size
41
Q

Advantages and disadvantages of RISC architecture?

A

A Level Computer Science (2 decks)

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