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EEE339 NP part > All cards > Flashcards

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1
Q

Propagation delay

A

Time between the input changing and the output responding.

Behaves as you would expect

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2
Q

Inertial delay

A

Exists due to capacitances in the gates. Similar to propagation delay, but if pulses are too small (shorter than the inertial delay) then the output will not respond to it

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3
Q

Transport delay

A

Time taken for a signal to propagate along a wire.

0 for an ASIC but matters for PCBs etc

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4
Q

Verilog ‘net’

A

Connect things together, like wires in am actual circuit

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5
Q

Verilog ‘registers’

A

Hold information. ‘Variable’ data type

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6
Q

Verilog ‘wires’

A

Default for ports. They take the value from the circuit driving them, but don’t store it. Like a multimeter in a circuit. ‘Net’ data type

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7
Q

Verilog ‘integers’

A

Used for numerical stuff. -ves are done using 2’s complement

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8
Q

Logic synthesis

A

Going from a behavioural model of how you want a system to behave, to an actual implementation of that system

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9
Q

Dataflow models

A

Models a combinational logic system as data with operations performed on it. Are synchronous

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10
Q

Register Transfer Level (RTL) dataflow model

A

A dataflow model that focuses on operations performed on data as it goes between registers

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11
Q

Transparent latch

A

A module with 2 inputs - 1 data in, 1 input boolean. The output will either equal the data in or maintain its current state, depending on the input boolean

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12
Q

Combinational behaviour

A

Output is ONLY a function of the present inputs (no memory)

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13
Q

Sequential behaviour

A

Output is a function of present AND past inputs (has memory)

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14
Q

Verilog ‘initial’ block

A

Runs once, never repeats. Similar to a setup loop. Single pass behaviour

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15
Q

Verilog ‘always’

A

Cyclic behaviour - can execute many times. Executes when there is an ‘event’ (change to a variable) on its sensitivity list

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16
Q

Blocking assignment

A

Evaluated and assigned in a single step. Execution flow in the procedure is ‘blocked’. Statement must be executed before further statements can execute

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17
Q

Non-blocking assignment

A

2 stage - RHS processed immediately but assignment is delayed. Waits until other evaluations in the current time step have been done. Flow is not blocked. Outcome is independent of the ordering of statements

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18
Q

Instruction Set Architecture (ISA)

A

The set of instructions (in assembly code) that a system can perform (e.g. ADD, MOV etc)

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19
Q

Arithmetic Logic Unit (ALU)

A

Made up of an arithmetic part and a logic part, with select lines to choose one. Receives DATA from memory or registers

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20
Q

Control Unit (CU)

A

Controls the interpretation of instructions (e.g. fetching operands). Fetches machine language INSTRUCTIONS from memory and decodes them

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21
Q

Von Neumann Architecture

A

Has a single memory interface used for both code and data. It is up to the programmer to make sure that the interpretation is correct

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22
Q

Harvard Architecture

A

Has 2 separate memory interfaces for data and code

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23
Q

Tristate buffer

A

3 output states - high, low or high-Z

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24
Q

Why is the (Memory) Address Register required if there is already a Program Counter

A

The AR can be used for holding both instructions and data- the AR is a convenient place to store the data. Also, latching the address of instructions in the AR means that the PC can be incremented at the same time as an instruction fetch

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25
Q

Why are bi-directional buffers needed to connect the data bus to memory chips?

A

Data goes between the CPU and memory via the bus.
When writing to memory: The buffers are needed to drive the memory because the CPU does not have the capacity to drive them on its own. The buffers are placed on the bus rather than the CPU itself because of power consumption limitations.
When reading from memory: The bus is noisy, so Schmitt triggers are used

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26
Q

Why is the Instruction Register necessary

A

It provides the input to the FSM, and this value needs to be consistent. The FSM output goes to the control path, so if the input to the FSM changed then operation would be unpredictable

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27
Q

Why does the Program Counter need access to the internal data bus?

A

In order to carry out jump instructions - a value has to be loaded in

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28
Q

Microcode

A

A sequence of hardware-level control words, used to implement higher-level machine code instructions. The microcode sequences are held in ROM, which is connected to control inputs of the CPU’s internal components.

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29
Q

Hardwired control

A

Instructions are implemented in hardware - e.g. a block of multipliers and adders to make up an instruction. An FSM picks between the blocks of logic to use, based on the op-code.

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30
Q

Give the benefits and disadvantages of microcode vs hardwired control

A

Hardwired control is faster, but it is in hardware so can only be changed by changing the hardware. It is better for RISC processors as there are fewer instructions. Microcode is easier to design and modify and is much better for complex instructions. But it is slower so it can be less efficient if complex instructions are rarely used.

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31
Q

Restoring division

A

‘restores’ the dividend to its previous (+ve) value when dividend - divisor is -ve

32
Q

Non-restoring division

A

Does not restore the dividend if it becomes -ve

33
Q

Program counter (PC)

A

Special register which stores the ADDRESS of the next instruction to be fetched

34
Q

Big endian

A

The most significant byte (not bit). Is put at the byte with the lowest adress

35
Q

Immediate addressing

A

The operand is a constant given in the instruction itself

36
Q

Base/displacement addressing

A

Operand is in a memory location, the address of which is the value found in a register plus a constant

37
Q

PC relative addressing

A

The value in the immediate field (of the instruction itself) gives an offset. This is added to the next PC value to give the address of the instruction to be fetched.

38
Q

Implied addressing mode (as determined by the bits in the instruction)

A

The operand is implied by the instruction. The instruction makes it obvious what the operand must be

39
Q

Immediate addressing mode (as determined by the bits in the instruction)

A

The operand IS the data given in the instruction

40
Q

Register addressing mode (as determined by the bits in the instruction)

A

Data can be found in a register in the processor

41
Q

Memory addressing mode (as determined by the bits in the instruction)

A

Operands are stored in memory

42
Q

Advantages and disadvantages of immediate addressing

A

+ Data can be fetched at the same time as the instruction
+ No need for a memory reference
+ Fast
- Only a constant can be supplied this way
- Value of the constant must be small enough to fit in the field

43
Q

Advantages and disadvantages of register addressing

A

+ Only needs a small address field (of the instruction)
+ Shorter instructions are possible
+ No memory access required - fast
+ Good for frequently accessed variables
- There aren’t that many registers available
- Limited address space is available

44
Q

Advantages and disadvantages of direct memory addressing

A

+ only takes one memory access to get the data
+ No calculations are required to find the address
+ Fast for global variables
- Address of global variables must be known when program is compiled
- Limited address space is available

45
Q

Flow control instructions

A 
Change the contents of the PC
Come in 3 types:
- HALT
- JUMP
- CALL
46
Q

JUMP flow control instruction

A

A straightforward change of the PC contents. Can be conditional or unconditional.

47
Q

CALL flow control instruction

A

Remembers the address of the next instruction (that would’ve been processed if the call hadn’t happened), does the stuff associated with the call then returns to the point in the program where it left off. Used for subroutines.

48
Q

What is in the stack frame

A
  • Return address
  • Passed parameters
  • Local variables
  • Returned variables
49
Q

Instruction Register (IR)

A

Holds instructions over multiple cycles. Holds the address of data (operands)

50
Q

Temporal locality principle

A

A location that has been accessed recently is likely to be accessed again soon

51
Q

Spatial locality principle

A

If a location has been accessed, the next location that must be accessed is likely to be nearby

52
Q

Cache line

A

The chunk of data that is transferred from memory to the cache in one go (shelf of books analogy)

53
Q

Content Addressable Memory (CAM)

A

The data stored in memory is made up of the data itself and a tag. When searching the cache, the tag is checked to see if the cache entry holds the required data. If the data is there, there is a hit. Used in cache memory systems

54
Q

Direct mapped cache

A

Each block in main memory is mapped to a single cache location - each block can ONLY go to that location.

55
Q

Give the benefits and disadvantages of a direct mapped cache

A

+ Simple, easy to implement

  • Shitty performance
  • If multiple memory blocks that use the same bit of cache keep being used, that part of the cache has to keep being cleared
  • Lots of cache misses
56
Q

Fully associative cache

A

Each block of memory is mapped to ANY cache location

57
Q

Give the benefits and disadvantages of a fully associative cache

A

+ Best performance
+ lots of flexibility
- Harder to implement
- You need to know the full address in order to locate a block (since the data could be anywhere)

58
Q

Set associative cache

A

Compromise between fully associative cache and direct mapped cache. Cache is split into sets that data from certain blocks of memory can access. Within a set, it is fully associative

59
Q

Give the benefits and disadvantages of a set associative cache

A
  • Can occasionally suffer similar drawbacks as direct mapped
    + Hardware fairly simple
    + Don’t have to search through the whole cache
    + You get the best of both worlds
    + You rock out the show
60
Q

IIR filter

A

Infinite Impulse Response filter

61
Q

FIR filter

A

Finite Impulse Response filter

62
Q

Recursive filter

A

Uses current inputs as well as past OUTPUT values to produce the current output

63
Q

Non-recursive filter

A

Only uses input values to produce the current output

64
Q

Which application is the Harvard architecture very often used in and why

A

DSP applications, because harvard architectures can result in higher processing throughput which effectively determines the bandwidth of the system

65
Q

What are the advantages that the Von Neumann architecture has over Harvard architecture, and vice versa

A 
VN advantages:
- Better flexibility
- Simpler hardware, especially the CU
- Only need to provide 1 memory interface
Harvard advantages:
- 2 memory interfaces means data memory accesses and code fetches can be overlapped, therefore greater processing throughput
- Doesn't suffer from VN bottleneck
- Good for DSP applications
66
Q

Why is each register to register move (e.g. A->B) given its own opcode, instead of using a single opcode for a generic register move and specifying the source and destination registers as operands?

A

You get much quicker speed of operation with multiple opcodes, because you only have to perform one memory access. With the other method, you would need one to get the opcode and then 2 more fetches to get the operands

67
Q

Outline the process of adding 2 floating point numbers together

A

The mantissa of the number with the smaller exponent is right shifted. The number of times it is shifted is determined by the difference between the higher exponent and the lower exponent. The mantissas can then be added as normal

68
Q

Passing parameters to a procedure BY REFERENCE

A

The address of the value is pushed onto the stack

69
Q

Passing parameters to a procedure BY VALUE

A

A COPY of the parameter is pushed onto the stack

70
Q

Give an advantage and disadvantage of passing parameters to a procedure by reference

A

+ Large data structures can be passed with using just one address, so can be faster
- The procedure is able to access the original data items in the calling program, so data integrity may be compromised

71
Q

Give an advantage and disadvantage of passing parameters to a procedure by value

A

+ The procedure is able to access and modify the value whilst maintaining the original value seen by the calling program
- For large amounts of data, there is a time penalty and a stack space penalty

72
Q

In a serial shift and add multiplier, what is the advantage of right shifting the accumulated partial product instead of left shifting the multiplicand?

A

It means you only have to provide an n-bit wide adder and an n-bit wide multiplicand register - instead of 2n-bit wide for both

73
Q

What do you have to do to the multiplicand if you want to carry out signed shift-and-add multiplication on an unsigned multiplier?

A

You have to ‘sign-extend’ the multiplicand - fill it in with 1s on the left hand side. Otherwise the shift-and-add multiplier will give the wrong answer

74
Q

LIFO

A

Last in First Out. Items are pushed on and popped off. Used for stack memory to run subroutines

75
Q

Pipelining

A

Break down circuitry into stages to improve speed

EEE339 NP part (1 decks)

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