Fetch Decode Execute Cycle

Question 1

Define Arithmetic Logic Unit (ALU)

Answer 1

Performs calculations like ADD, OR and shift operators

Question 2

Define Control Unit (CU)

Answer 2

Coordinates activities in CPU, memory and peripherals

Question 3

Define Clock

Answer 3

Continuous sequence of clock pulses to help CU through its operations

Question 4

Define registers

Answer 4

Fast chip memory for temporary storage of binary values

Question 5

Define Program Counter (PC)

Answer 5

Holds address of next instruction to be executed.

Question 6

Define Current Instruction Register (CIR)

Answer 6

Stores current instruction being run (in binary)

Question 7

Define General Purpose registers

Answer 7

Have no specific purpose. Can store binary numbers. Often used as temporary storage when performing arithmetic functions.

Question 8

Define Memory Address Register (MAR)

Answer 8

Holds address of memory location from which data will be read from or written to. This is processors direct connection to address bus for accessing main memory. Either address of next instruction or address of data to be used in an instruction

Question 9

Define Memory Buffer Register (MDR)

Answer 9

Temporarily stores data read from or written to memory.
Processors direct connect to data bus for accessing main memory. Can be next instruction to be fetched, or data to be used in a instruction

Question 10

Define Status Register (SR)

Answer 10

Contain bit that are set (1) or cleared (0) depending on result of instruction. One bit is set so an overflow could occur.

Question 11

Define Accumulator

Answer 11

Mainly used as register in CPU to store intermediate logical or arithmetical data in multistep calculations

Question 12

What is the fetch stage

Answer 12

1. Contents of PC copied into MAR
2. Passes address to MAR along the address bus
3. PC is incremented for next instruction
4. The CU does a memory read operation, allowing data of memory location to return along data bus back to the MDR
5. Contents in MDR is copied to the CIR

Question 13

What is the decode stage

Answer 13

6. Data in MDR passed to the CU which then decodes instructions, then signals other components the instruction to be completed

Question 14

What is the execute stage

Answer 14

7. Instruction executed, using ALU, or loading/saving data to/from main memory, if needed
8. SR is then updated

Question 15

Define an interrupt

Answer 15

A signal sent to processor from a program/external device that halts other processes until it is dealt with
If many occur at once deals with them in priority
Test for interrupts happen at end of FDE cycle

Question 16

Where does an interrupt signal go through

Answer 16

The control bus to the processor

Question 17

Define interrupt register

Answer 17

Each bit in Interrupt register indicate a specific interrupt

Question 18

How does computer handle an interrupt

Answer 18

Suspends what its doing, by storing contents of key registers on system stack. So once finished with interrupt can restore values from correct place.

Question 19

What is meant by Storing the volatile environment

Answer 19

The storing of key registers

Question 20

What is the Interrupt Service Routine (ISR)

Answer 20

A piece of code for each different type of interrupt.

Question 21

What are interrupt Vectors

Answer 21

Address that inform interrupt handlers where to find IRS. With all interrupts assigned number 0 to 255.
There is a vector table that has the code and so this is used to locate the memory address of appropriate code to run